u-boot-brain/arch/x86/dts/chromebook_link.dts
Simon Glass a86d45491e x86: dts: link: Move SPD info into the memory controller
The SDRAM SPD (Serial Presence Detect) information should be contained
with the SDRAM controller. This makes it easier for the controller to access
it and removes the need for a separate compatible string.

As a first step, move the information.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17 10:27:23 +08:00

330 lines
7.3 KiB
Plaintext

/dts-v1/;
/include/ "skeleton.dtsi"
/include/ "keyboard.dtsi"
/include/ "serial.dtsi"
/include/ "rtc.dtsi"
/include/ "tsc_timer.dtsi"
/ {
model = "Google Link";
compatible = "google,link", "intel,celeron-ivybridge";
aliases {
spi0 = &spi;
usb0 = &usb_0;
usb1 = &usb_1;
};
config {
silent_console = <0>;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "intel,core-gen3";
reg = <0>;
intel,apic-id = <0>;
};
cpu@1 {
device_type = "cpu";
compatible = "intel,core-gen3";
reg = <1>;
intel,apic-id = <1>;
};
cpu@2 {
device_type = "cpu";
compatible = "intel,core-gen3";
reg = <2>;
intel,apic-id = <2>;
};
cpu@3 {
device_type = "cpu";
compatible = "intel,core-gen3";
reg = <3>;
intel,apic-id = <3>;
};
};
chosen {
stdout-path = "/serial";
};
keyboard {
intel,duplicate-por;
};
pci {
compatible = "pci-x86";
#address-cells = <3>;
#size-cells = <2>;
u-boot,dm-pre-reloc;
ranges = <0x02000000 0x0 0xe0000000 0xe0000000 0 0x10000000
0x42000000 0x0 0xd0000000 0xd0000000 0 0x10000000
0x01000000 0x0 0x1000 0x1000 0 0xefff>;
northbridge@0,0 {
reg = <0x00000000 0 0 0 0>;
compatible = "intel,bd82x6x-northbridge";
u-boot,dm-pre-reloc;
spd {
compatible = "memory-spd";
#address-cells = <1>;
#size-cells = <0>;
elpida_4Gb_1600_x16 {
reg = <0>;
data = [92 10 0b 03 04 19 02 02
03 52 01 08 0a 00 fe 00
69 78 69 3c 69 11 18 81
20 08 3c 3c 01 40 83 81
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 0f 11 42 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 02 fe 00
11 52 00 00 00 07 7f 37
45 42 4a 32 30 55 47 36
45 42 55 30 2d 47 4e 2d
46 20 30 20 02 fe 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00];
};
samsung_4Gb_1600_1.35v_x16 {
reg = <1>;
data = [92 11 0b 03 04 19 02 02
03 11 01 08 0a 00 fe 00
69 78 69 3c 69 11 18 81
f0 0a 3c 3c 01 40 83 01
00 80 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 0f 11 02 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 80 ce 01
00 00 00 00 00 00 6a 04
4d 34 37 31 42 35 36 37
34 42 48 30 2d 59 4b 30
20 20 00 00 80 ce 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00];
};
micron_4Gb_1600_1.35v_x16 {
reg = <2>;
data = [92 11 0b 03 04 19 02 02
03 11 01 08 0a 00 fe 00
69 78 69 3c 69 11 18 81
20 08 3c 3c 01 40 83 05
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 0f 01 02 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 80 2c 00
00 00 00 00 00 00 ad 75
34 4b 54 46 32 35 36 36
34 48 5a 2d 31 47 36 45
31 20 45 31 80 2c 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff];
};
};
};
gma@2,0 {
reg = <0x00001000 0 0 0 0>;
compatible = "intel,gma";
intel,dp_hotplug = <0 0 0x06>;
intel,panel-port-select = <1>;
intel,panel-power-cycle-delay = <6>;
intel,panel-power-up-delay = <2000>;
intel,panel-power-down-delay = <500>;
intel,panel-power-backlight-on-delay = <2000>;
intel,panel-power-backlight-off-delay = <2000>;
intel,cpu-backlight = <0x00000200>;
intel,pch-backlight = <0x04000000>;
};
me@16,0 {
reg = <0x0000b000 0 0 0 0>;
compatible = "intel,me";
u-boot,dm-pre-reloc;
};
usb_1: usb@1a,0 {
reg = <0x0000d000 0 0 0 0>;
compatible = "ehci-pci";
};
usb_0: usb@1d,0 {
reg = <0x0000e800 0 0 0 0>;
compatible = "ehci-pci";
};
pch@1f,0 {
reg = <0x0000f800 0 0 0 0>;
compatible = "intel,bd82x6x", "intel,pch9";
u-boot,dm-pre-reloc;
#address-cells = <1>;
#size-cells = <1>;
intel,pirq-routing = <0x8b 0x8a 0x8b 0x8b
0x80 0x80 0x80 0x80>;
intel,gpi-routing = <0 0 0 0 0 0 0 2
1 0 0 0 0 0 0 0>;
/* Enable EC SMI source */
intel,alt-gp-smi-enable = <0x0100>;
spi: spi {
#address-cells = <1>;
#size-cells = <0>;
compatible = "intel,ich9-spi";
spi-flash@0 {
#size-cells = <1>;
#address-cells = <1>;
reg = <0>;
compatible = "winbond,w25q64",
"spi-flash";
memory-map = <0xff800000 0x00800000>;
rw-mrc-cache {
label = "rw-mrc-cache";
reg = <0x003e0000 0x00010000>;
};
};
};
gpio_a: gpioa {
compatible = "intel,ich6-gpio";
u-boot,dm-pre-reloc;
#gpio-cells = <2>;
gpio-controller;
reg = <0 0x10>;
bank-name = "A";
};
gpio_b: gpiob {
compatible = "intel,ich6-gpio";
u-boot,dm-pre-reloc;
#gpio-cells = <2>;
gpio-controller;
reg = <0x30 0x10>;
bank-name = "B";
};
gpio_c: gpioc {
compatible = "intel,ich6-gpio";
u-boot,dm-pre-reloc;
#gpio-cells = <2>;
gpio-controller;
reg = <0x40 0x10>;
bank-name = "C";
};
lpc {
compatible = "intel,bd82x6x-lpc";
#address-cells = <1>;
#size-cells = <0>;
u-boot,dm-pre-reloc;
intel,gen-dec = <0x800 0xfc 0x900 0xfc>;
cros-ec@200 {
compatible = "google,cros-ec";
reg = <0x204 1 0x200 1 0x880 0x80>;
/*
* Describes the flash memory within
* the EC
*/
#address-cells = <1>;
#size-cells = <1>;
flash@8000000 {
reg = <0x08000000 0x20000>;
erase-value = <0xff>;
};
};
};
};
sata@1f,2 {
compatible = "intel,pantherpoint-ahci";
reg = <0x0000fa00 0 0 0 0>;
u-boot,dm-pre-reloc;
intel,sata-mode = "ahci";
intel,sata-port-map = <1>;
intel,sata-port0-gen3-tx = <0x00880a7f>;
};
smbus: smbus@1f,3 {
compatible = "intel,ich-i2c";
reg = <0x0000fb00 0 0 0 0>;
u-boot,dm-pre-reloc;
};
};
tpm {
reg = <0xfed40000 0x5000>;
compatible = "infineon,slb9635lpc";
};
microcode {
update@0 {
#include "microcode/m12306a9_0000001b.dtsi"
};
};
};