mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-28 04:48:52 +09:00
![Simon Glass](/assets/img/avatar_default.png)
Convert this driver over to use driver model. Since all x86 platforms use it, move x86 to use driver model for SPI and SPI flash. Adjust all dependent code and remove the old x86 spi_init() function. Note that this does not make full use of the new PCI uclass as yet. We still scan the bus looking for the device. It should move to finding its details in the device tree. Signed-off-by: Simon Glass <sjg@chromium.org>
785 lines
20 KiB
C
785 lines
20 KiB
C
/*
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* Copyright (c) 2011-12 The Chromium OS Authors.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*
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* This file is derived from the flashrom project.
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*/
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#include <common.h>
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#include <dm.h>
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#include <errno.h>
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#include <malloc.h>
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#include <spi.h>
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#include <pci.h>
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#include <pci_ids.h>
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#include <asm/io.h>
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#include "ich.h"
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#define SPI_OPCODE_WREN 0x06
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#define SPI_OPCODE_FAST_READ 0x0b
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struct ich_spi_platdata {
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pci_dev_t dev; /* PCI device number */
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int ich_version; /* Controller version, 7 or 9 */
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bool use_sbase; /* Use SBASE instead of RCB */
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};
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struct ich_spi_priv {
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int ichspi_lock;
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int locked;
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int opmenu;
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int menubytes;
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void *base; /* Base of register set */
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int preop;
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int optype;
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int addr;
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int data;
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unsigned databytes;
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int status;
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int control;
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int bbar;
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uint32_t *pr; /* only for ich9 */
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int speed; /* pointer to speed control */
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ulong max_speed; /* Maximum bus speed in MHz */
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ulong cur_speed; /* Current bus speed */
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struct spi_trans trans; /* current transaction in progress */
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};
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static u8 ich_readb(struct ich_spi_priv *priv, int reg)
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{
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u8 value = readb(priv->base + reg);
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debug("read %2.2x from %4.4x\n", value, reg);
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return value;
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}
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static u16 ich_readw(struct ich_spi_priv *priv, int reg)
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{
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u16 value = readw(priv->base + reg);
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debug("read %4.4x from %4.4x\n", value, reg);
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return value;
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}
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static u32 ich_readl(struct ich_spi_priv *priv, int reg)
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{
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u32 value = readl(priv->base + reg);
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debug("read %8.8x from %4.4x\n", value, reg);
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return value;
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}
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static void ich_writeb(struct ich_spi_priv *priv, u8 value, int reg)
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{
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writeb(value, priv->base + reg);
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debug("wrote %2.2x to %4.4x\n", value, reg);
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}
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static void ich_writew(struct ich_spi_priv *priv, u16 value, int reg)
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{
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writew(value, priv->base + reg);
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debug("wrote %4.4x to %4.4x\n", value, reg);
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}
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static void ich_writel(struct ich_spi_priv *priv, u32 value, int reg)
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{
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writel(value, priv->base + reg);
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debug("wrote %8.8x to %4.4x\n", value, reg);
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}
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static void write_reg(struct ich_spi_priv *priv, const void *value,
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int dest_reg, uint32_t size)
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{
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memcpy_toio(priv->base + dest_reg, value, size);
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}
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static void read_reg(struct ich_spi_priv *priv, int src_reg, void *value,
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uint32_t size)
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{
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memcpy_fromio(value, priv->base + src_reg, size);
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}
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static void ich_set_bbar(struct ich_spi_priv *ctlr, uint32_t minaddr)
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{
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const uint32_t bbar_mask = 0x00ffff00;
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uint32_t ichspi_bbar;
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minaddr &= bbar_mask;
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ichspi_bbar = ich_readl(ctlr, ctlr->bbar) & ~bbar_mask;
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ichspi_bbar |= minaddr;
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ich_writel(ctlr, ichspi_bbar, ctlr->bbar);
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}
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/*
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* Check if this device ID matches one of supported Intel PCH devices.
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*
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* Return the ICH version if there is a match, or zero otherwise.
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*/
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static int get_ich_version(uint16_t device_id)
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{
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if (device_id == PCI_DEVICE_ID_INTEL_TGP_LPC ||
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device_id == PCI_DEVICE_ID_INTEL_ITC_LPC ||
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device_id == PCI_DEVICE_ID_INTEL_QRK_ILB)
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return 7;
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if ((device_id >= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MIN &&
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device_id <= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MAX) ||
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(device_id >= PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MIN &&
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device_id <= PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MAX) ||
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device_id == PCI_DEVICE_ID_INTEL_VALLEYVIEW_LPC ||
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device_id == PCI_DEVICE_ID_INTEL_LYNXPOINT_LPC)
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return 9;
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return 0;
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}
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/* @return 1 if the SPI flash supports the 33MHz speed */
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static int ich9_can_do_33mhz(pci_dev_t dev)
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{
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u32 fdod, speed;
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/* Observe SPI Descriptor Component Section 0 */
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pci_write_config_dword(dev, 0xb0, 0x1000);
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/* Extract the Write/Erase SPI Frequency from descriptor */
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pci_read_config_dword(dev, 0xb4, &fdod);
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/* Bits 23:21 have the fast read clock frequency, 0=20MHz, 1=33MHz */
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speed = (fdod >> 21) & 7;
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return speed == 1;
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}
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static int ich_find_spi_controller(struct ich_spi_platdata *ich)
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{
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int last_bus = pci_last_busno();
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int bus;
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if (last_bus == -1) {
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debug("No PCI busses?\n");
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return -ENODEV;
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}
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for (bus = 0; bus <= last_bus; bus++) {
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uint16_t vendor_id, device_id;
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uint32_t ids;
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pci_dev_t dev;
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dev = PCI_BDF(bus, 31, 0);
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pci_read_config_dword(dev, 0, &ids);
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vendor_id = ids;
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device_id = ids >> 16;
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if (vendor_id == PCI_VENDOR_ID_INTEL) {
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ich->dev = dev;
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ich->ich_version = get_ich_version(device_id);
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if (device_id == PCI_DEVICE_ID_INTEL_VALLEYVIEW_LPC)
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ich->use_sbase = true;
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return ich->ich_version == 0 ? -ENODEV : 0;
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}
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}
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debug("ICH SPI: No ICH found.\n");
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return -ENODEV;
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}
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static int ich_init_controller(struct ich_spi_platdata *plat,
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struct ich_spi_priv *ctlr)
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{
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uint8_t *rcrb; /* Root Complex Register Block */
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uint32_t rcba; /* Root Complex Base Address */
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uint32_t sbase_addr;
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uint8_t *sbase;
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pci_read_config_dword(plat->dev, 0xf0, &rcba);
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/* Bits 31-14 are the base address, 13-1 are reserved, 0 is enable. */
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rcrb = (uint8_t *)(rcba & 0xffffc000);
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/* SBASE is similar */
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pci_read_config_dword(plat->dev, 0x54, &sbase_addr);
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sbase = (uint8_t *)(sbase_addr & 0xfffffe00);
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if (plat->ich_version == 7) {
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struct ich7_spi_regs *ich7_spi;
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ich7_spi = (struct ich7_spi_regs *)(rcrb + 0x3020);
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ctlr->ichspi_lock = readw(&ich7_spi->spis) & SPIS_LOCK;
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ctlr->opmenu = offsetof(struct ich7_spi_regs, opmenu);
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ctlr->menubytes = sizeof(ich7_spi->opmenu);
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ctlr->optype = offsetof(struct ich7_spi_regs, optype);
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ctlr->addr = offsetof(struct ich7_spi_regs, spia);
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ctlr->data = offsetof(struct ich7_spi_regs, spid);
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ctlr->databytes = sizeof(ich7_spi->spid);
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ctlr->status = offsetof(struct ich7_spi_regs, spis);
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ctlr->control = offsetof(struct ich7_spi_regs, spic);
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ctlr->bbar = offsetof(struct ich7_spi_regs, bbar);
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ctlr->preop = offsetof(struct ich7_spi_regs, preop);
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ctlr->base = ich7_spi;
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} else if (plat->ich_version == 9) {
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struct ich9_spi_regs *ich9_spi;
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if (plat->use_sbase)
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ich9_spi = (struct ich9_spi_regs *)sbase;
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else
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ich9_spi = (struct ich9_spi_regs *)(rcrb + 0x3800);
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ctlr->ichspi_lock = readw(&ich9_spi->hsfs) & HSFS_FLOCKDN;
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ctlr->opmenu = offsetof(struct ich9_spi_regs, opmenu);
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ctlr->menubytes = sizeof(ich9_spi->opmenu);
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ctlr->optype = offsetof(struct ich9_spi_regs, optype);
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ctlr->addr = offsetof(struct ich9_spi_regs, faddr);
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ctlr->data = offsetof(struct ich9_spi_regs, fdata);
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ctlr->databytes = sizeof(ich9_spi->fdata);
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ctlr->status = offsetof(struct ich9_spi_regs, ssfs);
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ctlr->control = offsetof(struct ich9_spi_regs, ssfc);
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ctlr->speed = ctlr->control + 2;
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ctlr->bbar = offsetof(struct ich9_spi_regs, bbar);
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ctlr->preop = offsetof(struct ich9_spi_regs, preop);
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ctlr->pr = &ich9_spi->pr[0];
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ctlr->base = ich9_spi;
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} else {
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debug("ICH SPI: Unrecognised ICH version %d\n",
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plat->ich_version);
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return -EINVAL;
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}
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/* Work out the maximum speed we can support */
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ctlr->max_speed = 20000000;
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if (plat->ich_version == 9 && ich9_can_do_33mhz(plat->dev))
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ctlr->max_speed = 33000000;
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debug("ICH SPI: Version %d detected at %p, speed %ld\n",
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plat->ich_version, ctlr->base, ctlr->max_speed);
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ich_set_bbar(ctlr, 0);
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return 0;
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}
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static inline void spi_use_out(struct spi_trans *trans, unsigned bytes)
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{
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trans->out += bytes;
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trans->bytesout -= bytes;
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}
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static inline void spi_use_in(struct spi_trans *trans, unsigned bytes)
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{
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trans->in += bytes;
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trans->bytesin -= bytes;
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}
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static void spi_setup_type(struct spi_trans *trans, int data_bytes)
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{
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trans->type = 0xFF;
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/* Try to guess spi type from read/write sizes. */
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if (trans->bytesin == 0) {
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if (trans->bytesout + data_bytes > 4)
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/*
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* If bytesin = 0 and bytesout > 4, we presume this is
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* a write data operation, which is accompanied by an
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* address.
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*/
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trans->type = SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS;
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else
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trans->type = SPI_OPCODE_TYPE_WRITE_NO_ADDRESS;
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return;
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}
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if (trans->bytesout == 1) { /* and bytesin is > 0 */
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trans->type = SPI_OPCODE_TYPE_READ_NO_ADDRESS;
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return;
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}
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if (trans->bytesout == 4) /* and bytesin is > 0 */
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trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS;
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/* Fast read command is called with 5 bytes instead of 4 */
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if (trans->out[0] == SPI_OPCODE_FAST_READ && trans->bytesout == 5) {
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trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS;
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--trans->bytesout;
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}
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}
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static int spi_setup_opcode(struct ich_spi_priv *ctlr, struct spi_trans *trans)
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{
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uint16_t optypes;
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uint8_t opmenu[ctlr->menubytes];
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trans->opcode = trans->out[0];
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spi_use_out(trans, 1);
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if (!ctlr->ichspi_lock) {
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/* The lock is off, so just use index 0. */
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ich_writeb(ctlr, trans->opcode, ctlr->opmenu);
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optypes = ich_readw(ctlr, ctlr->optype);
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optypes = (optypes & 0xfffc) | (trans->type & 0x3);
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ich_writew(ctlr, optypes, ctlr->optype);
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return 0;
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} else {
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/* The lock is on. See if what we need is on the menu. */
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uint8_t optype;
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uint16_t opcode_index;
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/* Write Enable is handled as atomic prefix */
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if (trans->opcode == SPI_OPCODE_WREN)
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return 0;
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read_reg(ctlr, ctlr->opmenu, opmenu, sizeof(opmenu));
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for (opcode_index = 0; opcode_index < ctlr->menubytes;
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opcode_index++) {
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if (opmenu[opcode_index] == trans->opcode)
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break;
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}
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if (opcode_index == ctlr->menubytes) {
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printf("ICH SPI: Opcode %x not found\n",
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trans->opcode);
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return -EINVAL;
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}
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optypes = ich_readw(ctlr, ctlr->optype);
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optype = (optypes >> (opcode_index * 2)) & 0x3;
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if (trans->type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS &&
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optype == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS &&
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trans->bytesout >= 3) {
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/* We guessed wrong earlier. Fix it up. */
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trans->type = optype;
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}
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if (optype != trans->type) {
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printf("ICH SPI: Transaction doesn't fit type %d\n",
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optype);
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return -ENOSPC;
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}
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return opcode_index;
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}
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}
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static int spi_setup_offset(struct spi_trans *trans)
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{
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/* Separate the SPI address and data. */
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switch (trans->type) {
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case SPI_OPCODE_TYPE_READ_NO_ADDRESS:
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case SPI_OPCODE_TYPE_WRITE_NO_ADDRESS:
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return 0;
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case SPI_OPCODE_TYPE_READ_WITH_ADDRESS:
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case SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS:
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trans->offset = ((uint32_t)trans->out[0] << 16) |
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((uint32_t)trans->out[1] << 8) |
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((uint32_t)trans->out[2] << 0);
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spi_use_out(trans, 3);
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return 1;
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default:
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printf("Unrecognized SPI transaction type %#x\n", trans->type);
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return -EPROTO;
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}
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}
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/*
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* Wait for up to 6s til status register bit(s) turn 1 (in case wait_til_set
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* below is true) or 0. In case the wait was for the bit(s) to set - write
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* those bits back, which would cause resetting them.
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*
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* Return the last read status value on success or -1 on failure.
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*/
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static int ich_status_poll(struct ich_spi_priv *ctlr, u16 bitmask,
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int wait_til_set)
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{
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int timeout = 600000; /* This will result in 6s */
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u16 status = 0;
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while (timeout--) {
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status = ich_readw(ctlr, ctlr->status);
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if (wait_til_set ^ ((status & bitmask) == 0)) {
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if (wait_til_set) {
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ich_writew(ctlr, status & bitmask,
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ctlr->status);
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}
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return status;
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}
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udelay(10);
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}
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printf("ICH SPI: SCIP timeout, read %x, expected %x\n",
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status, bitmask);
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return -ETIMEDOUT;
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}
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static int ich_spi_xfer(struct udevice *dev, unsigned int bitlen,
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const void *dout, void *din, unsigned long flags)
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{
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struct udevice *bus = dev_get_parent(dev);
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struct ich_spi_priv *ctlr = dev_get_priv(bus);
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uint16_t control;
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int16_t opcode_index;
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int with_address;
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int status;
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int bytes = bitlen / 8;
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struct spi_trans *trans = &ctlr->trans;
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unsigned type = flags & (SPI_XFER_BEGIN | SPI_XFER_END);
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int using_cmd = 0;
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int ret;
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/* Ee don't support writing partial bytes. */
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if (bitlen % 8) {
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debug("ICH SPI: Accessing partial bytes not supported\n");
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return -EPROTONOSUPPORT;
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}
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/* An empty end transaction can be ignored */
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if (type == SPI_XFER_END && !dout && !din)
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return 0;
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if (type & SPI_XFER_BEGIN)
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memset(trans, '\0', sizeof(*trans));
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/* Dp we need to come back later to finish it? */
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if (dout && type == SPI_XFER_BEGIN) {
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if (bytes > ICH_MAX_CMD_LEN) {
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debug("ICH SPI: Command length limit exceeded\n");
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return -ENOSPC;
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}
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memcpy(trans->cmd, dout, bytes);
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trans->cmd_len = bytes;
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debug("ICH SPI: Saved %d bytes\n", bytes);
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return 0;
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}
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/*
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* We process a 'middle' spi_xfer() call, which has no
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* SPI_XFER_BEGIN/END, as an independent transaction as if it had
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* an end. We therefore repeat the command. This is because ICH
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* seems to have no support for this, or because interest (in digging
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* out the details and creating a special case in the code) is low.
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*/
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if (trans->cmd_len) {
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trans->out = trans->cmd;
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trans->bytesout = trans->cmd_len;
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using_cmd = 1;
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debug("ICH SPI: Using %d bytes\n", trans->cmd_len);
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} else {
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trans->out = dout;
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trans->bytesout = dout ? bytes : 0;
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}
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trans->in = din;
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trans->bytesin = din ? bytes : 0;
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/* There has to always at least be an opcode. */
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if (!trans->bytesout) {
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debug("ICH SPI: No opcode for transfer\n");
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return -EPROTO;
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}
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ret = ich_status_poll(ctlr, SPIS_SCIP, 0);
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if (ret < 0)
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return ret;
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|
|
ich_writew(ctlr, SPIS_CDS | SPIS_FCERR, ctlr->status);
|
|
|
|
spi_setup_type(trans, using_cmd ? bytes : 0);
|
|
opcode_index = spi_setup_opcode(ctlr, trans);
|
|
if (opcode_index < 0)
|
|
return -EINVAL;
|
|
with_address = spi_setup_offset(trans);
|
|
if (with_address < 0)
|
|
return -EINVAL;
|
|
|
|
if (trans->opcode == SPI_OPCODE_WREN) {
|
|
/*
|
|
* Treat Write Enable as Atomic Pre-Op if possible
|
|
* in order to prevent the Management Engine from
|
|
* issuing a transaction between WREN and DATA.
|
|
*/
|
|
if (!ctlr->ichspi_lock)
|
|
ich_writew(ctlr, trans->opcode, ctlr->preop);
|
|
return 0;
|
|
}
|
|
|
|
if (ctlr->speed && ctlr->max_speed >= 33000000) {
|
|
int byte;
|
|
|
|
byte = ich_readb(ctlr, ctlr->speed);
|
|
if (ctlr->cur_speed >= 33000000)
|
|
byte |= SSFC_SCF_33MHZ;
|
|
else
|
|
byte &= ~SSFC_SCF_33MHZ;
|
|
ich_writeb(ctlr, byte, ctlr->speed);
|
|
}
|
|
|
|
/* See if we have used up the command data */
|
|
if (using_cmd && dout && bytes) {
|
|
trans->out = dout;
|
|
trans->bytesout = bytes;
|
|
debug("ICH SPI: Moving to data, %d bytes\n", bytes);
|
|
}
|
|
|
|
/* Preset control fields */
|
|
control = ich_readw(ctlr, ctlr->control);
|
|
control &= ~SSFC_RESERVED;
|
|
control = SPIC_SCGO | ((opcode_index & 0x07) << 4);
|
|
|
|
/* Issue atomic preop cycle if needed */
|
|
if (ich_readw(ctlr, ctlr->preop))
|
|
control |= SPIC_ACS;
|
|
|
|
if (!trans->bytesout && !trans->bytesin) {
|
|
/* SPI addresses are 24 bit only */
|
|
if (with_address) {
|
|
ich_writel(ctlr, trans->offset & 0x00FFFFFF,
|
|
ctlr->addr);
|
|
}
|
|
/*
|
|
* This is a 'no data' command (like Write Enable), its
|
|
* bitesout size was 1, decremented to zero while executing
|
|
* spi_setup_opcode() above. Tell the chip to send the
|
|
* command.
|
|
*/
|
|
ich_writew(ctlr, control, ctlr->control);
|
|
|
|
/* wait for the result */
|
|
status = ich_status_poll(ctlr, SPIS_CDS | SPIS_FCERR, 1);
|
|
if (status < 0)
|
|
return status;
|
|
|
|
if (status & SPIS_FCERR) {
|
|
debug("ICH SPI: Command transaction error\n");
|
|
return -EIO;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* Check if this is a write command atempting to transfer more bytes
|
|
* than the controller can handle. Iterations for writes are not
|
|
* supported here because each SPI write command needs to be preceded
|
|
* and followed by other SPI commands, and this sequence is controlled
|
|
* by the SPI chip driver.
|
|
*/
|
|
if (trans->bytesout > ctlr->databytes) {
|
|
debug("ICH SPI: Too much to write. This should be prevented by the driver's max_write_size?\n");
|
|
return -EPROTO;
|
|
}
|
|
|
|
/*
|
|
* Read or write up to databytes bytes at a time until everything has
|
|
* been sent.
|
|
*/
|
|
while (trans->bytesout || trans->bytesin) {
|
|
uint32_t data_length;
|
|
|
|
/* SPI addresses are 24 bit only */
|
|
ich_writel(ctlr, trans->offset & 0x00FFFFFF, ctlr->addr);
|
|
|
|
if (trans->bytesout)
|
|
data_length = min(trans->bytesout, ctlr->databytes);
|
|
else
|
|
data_length = min(trans->bytesin, ctlr->databytes);
|
|
|
|
/* Program data into FDATA0 to N */
|
|
if (trans->bytesout) {
|
|
write_reg(ctlr, trans->out, ctlr->data, data_length);
|
|
spi_use_out(trans, data_length);
|
|
if (with_address)
|
|
trans->offset += data_length;
|
|
}
|
|
|
|
/* Add proper control fields' values */
|
|
control &= ~((ctlr->databytes - 1) << 8);
|
|
control |= SPIC_DS;
|
|
control |= (data_length - 1) << 8;
|
|
|
|
/* write it */
|
|
ich_writew(ctlr, control, ctlr->control);
|
|
|
|
/* Wait for Cycle Done Status or Flash Cycle Error. */
|
|
status = ich_status_poll(ctlr, SPIS_CDS | SPIS_FCERR, 1);
|
|
if (status < 0)
|
|
return status;
|
|
|
|
if (status & SPIS_FCERR) {
|
|
debug("ICH SPI: Data transaction error\n");
|
|
return -EIO;
|
|
}
|
|
|
|
if (trans->bytesin) {
|
|
read_reg(ctlr, ctlr->data, trans->in, data_length);
|
|
spi_use_in(trans, data_length);
|
|
if (with_address)
|
|
trans->offset += data_length;
|
|
}
|
|
}
|
|
|
|
/* Clear atomic preop now that xfer is done */
|
|
ich_writew(ctlr, 0, ctlr->preop);
|
|
|
|
return 0;
|
|
}
|
|
|
|
|
|
/*
|
|
* This uses the SPI controller from the Intel Cougar Point and Panther Point
|
|
* PCH to write-protect portions of the SPI flash until reboot. The changes
|
|
* don't actually take effect until the HSFS[FLOCKDN] bit is set, but that's
|
|
* done elsewhere.
|
|
*/
|
|
int spi_write_protect_region(struct udevice *dev, uint32_t lower_limit,
|
|
uint32_t length, int hint)
|
|
{
|
|
struct udevice *bus = dev->parent;
|
|
struct ich_spi_priv *ctlr = dev_get_priv(bus);
|
|
uint32_t tmplong;
|
|
uint32_t upper_limit;
|
|
|
|
if (!ctlr->pr) {
|
|
printf("%s: operation not supported on this chipset\n",
|
|
__func__);
|
|
return -ENOSYS;
|
|
}
|
|
|
|
if (length == 0 ||
|
|
lower_limit > (0xFFFFFFFFUL - length) + 1 ||
|
|
hint < 0 || hint > 4) {
|
|
printf("%s(0x%x, 0x%x, %d): invalid args\n", __func__,
|
|
lower_limit, length, hint);
|
|
return -EPERM;
|
|
}
|
|
|
|
upper_limit = lower_limit + length - 1;
|
|
|
|
/*
|
|
* Determine bits to write, as follows:
|
|
* 31 Write-protection enable (includes erase operation)
|
|
* 30:29 reserved
|
|
* 28:16 Upper Limit (FLA address bits 24:12, with 11:0 == 0xfff)
|
|
* 15 Read-protection enable
|
|
* 14:13 reserved
|
|
* 12:0 Lower Limit (FLA address bits 24:12, with 11:0 == 0x000)
|
|
*/
|
|
tmplong = 0x80000000 |
|
|
((upper_limit & 0x01fff000) << 4) |
|
|
((lower_limit & 0x01fff000) >> 12);
|
|
|
|
printf("%s: writing 0x%08x to %p\n", __func__, tmplong,
|
|
&ctlr->pr[hint]);
|
|
ctlr->pr[hint] = tmplong;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int ich_spi_probe(struct udevice *bus)
|
|
{
|
|
struct ich_spi_platdata *plat = dev_get_platdata(bus);
|
|
struct ich_spi_priv *priv = dev_get_priv(bus);
|
|
uint8_t bios_cntl;
|
|
int ret;
|
|
|
|
ret = ich_init_controller(plat, priv);
|
|
if (ret)
|
|
return ret;
|
|
/*
|
|
* Disable the BIOS write protect so write commands are allowed. On
|
|
* v9, deassert SMM BIOS Write Protect Disable.
|
|
*/
|
|
if (plat->use_sbase) {
|
|
struct ich9_spi_regs *ich9_spi;
|
|
|
|
ich9_spi = priv->base;
|
|
bios_cntl = ich_readb(priv, ich9_spi->bcr);
|
|
bios_cntl &= ~(1 << 5); /* clear Enable InSMM_STS (EISS) */
|
|
bios_cntl |= 1; /* Write Protect Disable (WPD) */
|
|
ich_writeb(priv, bios_cntl, ich9_spi->bcr);
|
|
} else {
|
|
pci_read_config_byte(plat->dev, 0xdc, &bios_cntl);
|
|
if (plat->ich_version == 9)
|
|
bios_cntl &= ~(1 << 5);
|
|
pci_write_config_byte(plat->dev, 0xdc, bios_cntl | 0x1);
|
|
}
|
|
|
|
priv->cur_speed = priv->max_speed;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int ich_spi_ofdata_to_platdata(struct udevice *bus)
|
|
{
|
|
struct ich_spi_platdata *plat = dev_get_platdata(bus);
|
|
int ret;
|
|
|
|
ret = ich_find_spi_controller(plat);
|
|
if (ret)
|
|
return ret;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int ich_spi_set_speed(struct udevice *bus, uint speed)
|
|
{
|
|
struct ich_spi_priv *priv = dev_get_priv(bus);
|
|
|
|
priv->cur_speed = speed;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int ich_spi_set_mode(struct udevice *bus, uint mode)
|
|
{
|
|
debug("%s: mode=%d\n", __func__, mode);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int ich_spi_child_pre_probe(struct udevice *dev)
|
|
{
|
|
struct udevice *bus = dev_get_parent(dev);
|
|
struct ich_spi_platdata *plat = dev_get_platdata(bus);
|
|
struct ich_spi_priv *priv = dev_get_priv(bus);
|
|
struct spi_slave *slave = dev_get_parentdata(dev);
|
|
|
|
/*
|
|
* Yes this controller can only write a small number of bytes at
|
|
* once! The limit is typically 64 bytes.
|
|
*/
|
|
slave->max_write_size = priv->databytes;
|
|
/*
|
|
* ICH 7 SPI controller only supports array read command
|
|
* and byte program command for SST flash
|
|
*/
|
|
if (plat->ich_version == 7) {
|
|
slave->op_mode_rx = SPI_OPM_RX_AS;
|
|
slave->op_mode_tx = SPI_OPM_TX_BP;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct dm_spi_ops ich_spi_ops = {
|
|
.xfer = ich_spi_xfer,
|
|
.set_speed = ich_spi_set_speed,
|
|
.set_mode = ich_spi_set_mode,
|
|
/*
|
|
* cs_info is not needed, since we require all chip selects to be
|
|
* in the device tree explicitly
|
|
*/
|
|
};
|
|
|
|
static const struct udevice_id ich_spi_ids[] = {
|
|
{ .compatible = "intel,ich-spi" },
|
|
{ }
|
|
};
|
|
|
|
U_BOOT_DRIVER(ich_spi) = {
|
|
.name = "ich_spi",
|
|
.id = UCLASS_SPI,
|
|
.of_match = ich_spi_ids,
|
|
.ops = &ich_spi_ops,
|
|
.ofdata_to_platdata = ich_spi_ofdata_to_platdata,
|
|
.platdata_auto_alloc_size = sizeof(struct ich_spi_platdata),
|
|
.priv_auto_alloc_size = sizeof(struct ich_spi_priv),
|
|
.child_pre_probe = ich_spi_child_pre_probe,
|
|
.probe = ich_spi_probe,
|
|
};
|