mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-26 04:49:42 +09:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
131 lines
2.9 KiB
C
131 lines
2.9 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* AU1X00 UART support
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*
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* Hardcoded to UART 0 for now
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* Speed and options also hardcoded to 115200 8N1
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*
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* Copyright (c) 2003 Thomas.Lange@corelatus.se
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*/
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#include <config.h>
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#include <common.h>
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#include <mach/au1x00.h>
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#include <serial.h>
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#include <linux/compiler.h>
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/******************************************************************************
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*
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* serial_init - initialize a channel
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*
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* This routine initializes the number of data bits, parity
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* and set the selected baud rate. Interrupts are disabled.
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* Set the modem control signals if the option is selected.
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*
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* RETURNS: N/A
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*/
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static int au1x00_serial_init(void)
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{
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volatile u32 *uart_fifoctl = (volatile u32*)(UART0_ADDR+UART_FCR);
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volatile u32 *uart_enable = (volatile u32*)(UART0_ADDR+UART_ENABLE);
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/* Enable clocks first */
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*uart_enable = UART_EN_CE;
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/* Then release reset */
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/* Must release reset before setting other regs */
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*uart_enable = UART_EN_CE|UART_EN_E;
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/* Activate fifos, reset tx and rx */
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/* Set tx trigger level to 12 */
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*uart_fifoctl = UART_FCR_ENABLE_FIFO|UART_FCR_CLEAR_RCVR|
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UART_FCR_CLEAR_XMIT|UART_FCR_T_TRIGGER_12;
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serial_setbrg();
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return 0;
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}
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static void au1x00_serial_setbrg(void)
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{
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volatile u32 *uart_clk = (volatile u32*)(UART0_ADDR+UART_CLK);
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volatile u32 *uart_lcr = (volatile u32*)(UART0_ADDR+UART_LCR);
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volatile u32 *sys_powerctrl = (u32 *)SYS_POWERCTRL;
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int sd;
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int divisorx2;
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/* sd is system clock divisor */
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/* see section 10.4.5 in au1550 datasheet */
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sd = (*sys_powerctrl & 0x03) + 2;
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/* calulate 2x baudrate and round */
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divisorx2 = ((CONFIG_SYS_MIPS_TIMER_FREQ/(sd * 16 * CONFIG_BAUDRATE)));
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if (divisorx2 & 0x01)
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divisorx2 = divisorx2 + 1;
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*uart_clk = divisorx2 / 2;
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/* Set parity, stop bits and word length to 8N1 */
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*uart_lcr = UART_LCR_WLEN8;
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}
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static void au1x00_serial_putc(const char c)
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{
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volatile u32 *uart_lsr = (volatile u32*)(UART0_ADDR+UART_LSR);
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volatile u32 *uart_tx = (volatile u32*)(UART0_ADDR+UART_TX);
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if (c == '\n')
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au1x00_serial_putc('\r');
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/* Wait for fifo to shift out some bytes */
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while((*uart_lsr&UART_LSR_THRE)==0);
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*uart_tx = (u32)c;
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}
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static int au1x00_serial_getc(void)
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{
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volatile u32 *uart_rx = (volatile u32*)(UART0_ADDR+UART_RX);
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char c;
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while (!serial_tstc());
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c = (*uart_rx&0xFF);
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return c;
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}
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static int au1x00_serial_tstc(void)
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{
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volatile u32 *uart_lsr = (volatile u32*)(UART0_ADDR+UART_LSR);
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if(*uart_lsr&UART_LSR_DR){
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/* Data in rfifo */
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return(1);
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}
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return 0;
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}
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static struct serial_device au1x00_serial_drv = {
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.name = "au1x00_serial",
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.start = au1x00_serial_init,
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.stop = NULL,
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.setbrg = au1x00_serial_setbrg,
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.putc = au1x00_serial_putc,
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.puts = default_serial_puts,
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.getc = au1x00_serial_getc,
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.tstc = au1x00_serial_tstc,
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};
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void au1x00_serial_initialize(void)
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{
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serial_register(&au1x00_serial_drv);
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}
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__weak struct serial_device *default_serial_console(void)
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{
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return &au1x00_serial_drv;
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}
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