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https://github.com/brain-hackers/u-boot-brain
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![Wolfgang Denk](/assets/img/avatar_default.png)
Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
72 lines
2.1 KiB
INI
72 lines
2.1 KiB
INI
#
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# Copyright (C) 2012 Albert ARIBAUD <albert.u.boot@aribaud.net>
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#
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# Based on netspace_v2 kwbimage.cfg:
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# Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
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#
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# Based on Kirkwood support:
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# (C) Copyright 2009
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# Marvell Semiconductor <www.marvell.com>
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# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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# Refer doc/README.kwbimage for more details about how-to configure
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# and create kirkwood boot image
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#
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# Boot Media configurations
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BOOT_FROM nand # Boot from NAND flash
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NAND_PAGE_SIZE 800
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# SOC registers configuration using bootrom header extension
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# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
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# Values taken from image original LaCie U-Boot header dump!
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# Configure RGMII-0 interface pad voltage to 1.8V
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DATA 0xFFD100e0 0x1B1B1B9B
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#Dram initalization for SINGLE x16 CL=5 @ 400MHz
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DATA 0xFFD01400 0x43000c30 # DDR Configuration register
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DATA 0xFFD01404 0x37743000 # DDR Controller Control Low
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DATA 0xFFD01408 0x11012228 # DDR Timing (Low) (active cycles value +1)
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DATA 0xFFD0140C 0x00000A19 # DDR Timing (High)
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DATA 0xFFD01410 0x0000CCCC # DDR Address Control
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DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
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DATA 0xFFD01418 0x00000000 # DDR Operation
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DATA 0xFFD0141C 0x00000662 # DDR Mode
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DATA 0xFFD01420 0x00000004 # DDR Extended Mode
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DATA 0xFFD01424 0x0000F07F # DDR Controller Control High
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DATA 0xFFD01428 0x00096630 # DDR2 ODT Read Timing (default values)
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DATA 0xFFD0147C 0x00009663 # DDR2 ODT Write Timing (default values)
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DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size
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DATA 0xFFD01508 0x00000000 # CS[1]n Base address to 0x0
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DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled
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DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled
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DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
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DATA 0xFFD01494 0x00120012 # DDR ODT Control (Low)
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DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
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DATA 0xFFD0149C 0x0000E40F # CPU ODT Control
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DATA 0xFFD01480 0x00000001 # DDR Initialization Control
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DATA 0xFFD20134 0x66666666
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DATA 0xFFD20138 0x66666666
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DATA 0xFFD10000 0x01112222
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DATA 0xFFD1000C 0x00000000
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DATA 0xFFD10104 0x00000000
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DATA 0xFFD10100 0x40000000
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# End of Header extension
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DATA 0x0 0x0
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