Tom Warren b77c3547e8 Tegra114: fdt: Update DT files with I2C info for T114/Dalmore ... T114, like T30, does not have a separate/different DVC (power I2C) controller like T20 - all 5 I2C controllers are identical, but I2C5 is used to designate the controller intended for power control (PWR_I2C in the schematics). PWR_I2C is set to 400KHz. Signed-off-by: Tom Warren <twarren@nvidia.com> Acked-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>		2013-03-14 11:06:41 -07:00
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tegra20-harmony.dts	tegra: fdt: sort dts files	2013-01-17 09:07:34 -07:00
tegra20-seaboard.dts	tegra: fdt: add back missing host1x node	2013-02-11 10:35:23 -07:00
tegra20-ventana.dts	tegra: fdt: remove clocks nodes	2013-01-17 09:07:23 -07:00
tegra20-whistler.dts	tegra: fdt: remove clocks nodes	2013-01-17 09:07:23 -07:00
tegra30-cardhu.dts	tegra30: fdt: add SPI SLINK nodes	2013-02-11 10:35:24 -07:00
tegra114-dalmore.dts	Tegra114: fdt: Update DT files with I2C info for T114/Dalmore	2013-03-14 11:06:41 -07:00