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c7ea243cc0
In order to avoid code duplication, move the DDR3 initialization to the common place under imx-common. Currently ROW_DIFF and COL_DIFF can be chosen from the board file. The JEDEC timings are specified using a common ddr3_jedec_timings structure. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
73 lines
1.1 KiB
C
73 lines
1.1 KiB
C
/*
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* Copyright (C) 2015
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* Toradex, Inc.
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*
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* Authors: Stefan Agner
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* Sanchayan Maity
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __ASM_ARCH_VF610_DDRMC_H
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#define __ASM_ARCH_VF610_DDRMC_H
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struct ddrmc_lvl_info {
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u16 wrlvl_reg_en;
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u16 wrlvl_dl_0;
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u16 wrlvl_dl_1;
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u16 rdlvl_gt_reg_en;
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u16 rdlvl_gt_dl_0;
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u16 rdlvl_gt_dl_1;
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u16 rdlvl_reg_en;
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u16 rdlvl_dl_0;
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u16 rdlvl_dl_1;
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};
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struct ddr3_jedec_timings {
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u8 tinit;
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u32 trst_pwron;
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u32 cke_inactive;
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u8 wrlat;
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u8 caslat_lin;
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u8 trc;
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u8 trrd;
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u8 tccd;
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u8 tfaw;
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u8 trp;
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u8 twtr;
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u8 tras_min;
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u8 tmrd;
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u8 trtp;
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u32 tras_max;
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u8 tmod;
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u8 tckesr;
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u8 tcke;
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u8 trcd_int;
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u8 tdal;
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u16 tdll;
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u8 trp_ab;
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u16 tref;
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u8 trfc;
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u8 tpdex;
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u8 txpdll;
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u8 txsnr;
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u16 txsr;
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u8 cksrx;
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u8 cksre;
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u16 zqcl;
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u16 zqinit;
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u8 zqcs;
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u8 ref_per_zq;
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u8 aprebit;
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u8 wlmrd;
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u8 wldqsen;
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};
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void ddrmc_setup_iomux(void);
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void ddrmc_phy_init(void);
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void ddrmc_ctrl_init_ddr3(struct ddr3_jedec_timings const *timings,
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struct ddrmc_lvl_info *lvl,
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int col_diff, int row_diff);
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#endif
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