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https://github.com/brain-hackers/u-boot-brain
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72a087e047
Patch by Haavard Skinnemoen, 06 Sep 2006 This patch adds support for the AT32AP CPU family and the AT32AP7000 chip, which is the first chip implementing the AVR32 architecture. The AT32AP CPU core is a high-performance implementation featuring a 7-stage pipeline, separate instruction- and data caches, and a MMU. For more information, please see the "AVR32 AP Technical Reference": http://www.atmel.com/dyn/resources/prod_documents/doc32001.pdf In addition to this, the AT32AP7000 chip comes with a large set of integrated peripherals, many of which are shared with the AT91 series of ARM-based microcontrollers from Atmel. Full data sheet is available here: http://www.atmel.com/dyn/resources/prod_documents/doc32003.pdf Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
147 lines
3.1 KiB
C
147 lines
3.1 KiB
C
/*
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* Copyright (C) 2005-2006 Atmel Corporation
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef _ASM_AVR32_ARCH_PM_H
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#define _ASM_AVR32_ARCH_PM_H
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#include <config.h>
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enum clock_domain_id {
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CLOCK_CPU,
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CLOCK_HSB,
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CLOCK_PBA,
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CLOCK_PBB,
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NR_CLOCK_DOMAINS,
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};
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enum resource_type {
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RESOURCE_GPIO,
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RESOURCE_CLOCK,
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};
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enum gpio_func {
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GPIO_FUNC_GPIO,
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GPIO_FUNC_A,
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GPIO_FUNC_B,
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};
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enum device_id {
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DEVICE_HEBI,
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DEVICE_PBA_BRIDGE,
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DEVICE_PBB_BRIDGE,
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DEVICE_HRAMC,
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/* GPIO controllers must be kept together */
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DEVICE_PIOA,
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DEVICE_PIOB,
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DEVICE_PIOC,
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DEVICE_PIOD,
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DEVICE_PIOE,
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DEVICE_SM,
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DEVICE_INTC,
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DEVICE_HMATRIX,
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#if defined(CFG_HPDC)
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DEVICE_HPDC,
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#endif
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#if defined(CFG_MACB0)
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DEVICE_MACB0,
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#endif
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#if defined(CFG_MACB1)
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DEVICE_MACB1,
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#endif
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#if defined(CFG_LCDC)
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DEVICE_LCDC,
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#endif
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#if defined(CFG_USART0)
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DEVICE_USART0,
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#endif
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#if defined(CFG_USART1)
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DEVICE_USART1,
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#endif
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#if defined(CFG_USART2)
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DEVICE_USART2,
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#endif
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#if defined(CFG_USART3)
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DEVICE_USART3,
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#endif
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#if defined(CFG_MMCI)
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DEVICE_MMCI,
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#endif
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#if defined(CFG_DMAC)
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DEVICE_DMAC,
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#endif
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NR_DEVICES,
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NO_DEVICE = -1,
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};
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struct resource {
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enum resource_type type;
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union {
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struct {
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unsigned long base;
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} iomem;
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struct {
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unsigned char nr_pins;
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enum device_id gpio_dev;
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enum gpio_func func;
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unsigned short start;
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} gpio;
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struct {
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enum clock_domain_id id;
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unsigned char index;
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} clock;
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} u;
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};
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struct device {
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void *regs;
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unsigned int nr_resources;
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const struct resource *resource;
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};
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struct clock_domain {
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unsigned short reg;
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enum clock_domain_id id;
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enum device_id bridge;
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};
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extern const struct device chip_device[NR_DEVICES];
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extern const struct clock_domain chip_clock[NR_CLOCK_DOMAINS];
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/**
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* Set up PIO, clock management and I/O memory for a device.
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*/
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const struct device *get_device(enum device_id devid);
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void put_device(const struct device *dev);
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int gpio_set_func(enum device_id gpio_devid, unsigned int start,
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unsigned int nr_pins, enum gpio_func func);
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void gpio_free(enum device_id gpio_devid, unsigned int start,
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unsigned int nr_pins);
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void pm_init(void);
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int pm_enable_clock(enum clock_domain_id id, unsigned int index);
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void pm_disable_clock(enum clock_domain_id id, unsigned int index);
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unsigned long pm_get_clock_freq(enum clock_domain_id domain);
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void cpu_enable_sdram(void);
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#endif /* _ASM_AVR32_ARCH_PM_H */
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