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https://github.com/brain-hackers/u-boot-brain
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a6d7e8c914
At present there is only one Kconfig option CONFIG_SIFIVE_CLINT to
control the enabling of SiFive CLINT support in both SPL (M-mode)
and U-Boot proper (S-mode). So for a typical SPL config that the
SiFive CLINT driver is enabled in both SPL and U-Boot proper, that
means the S-mode U-Boot tries to access the memory-mapped CLINT
registers directly, instead of the normal 'rdtime' instruction.
This was not a problem before, as the hardware does not forbid the
access from S-mode. However this becomes an issue now with OpenSBI
commit 8b569803475e ("lib: utils/sys: Add CLINT memregion in the root domain")
that the SiFive CLINT register space is protected by PMP for M-mode
access only. U-Boot proper does not boot any more with the latest
OpenSBI, that access exceptions are fired forever from U-Boot when
trying to read the timer value via the SiFive CLINT driver in U-Boot.
To solve this, we need to split current SiFive CLINT support between
SPL and U-Boot proper, using 2 separate Kconfig options.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
53 lines
878 B
Plaintext
53 lines
878 B
Plaintext
# SPDX-License-Identifier: GPL-2.0+
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#
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# Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
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config SIFIVE_FU540
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bool
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select ARCH_EARLY_INIT_R
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select SUPPORT_SPL
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select RAM
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select SPL_RAM if SPL
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imply CPU
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imply CPU_RISCV
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imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE)
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imply SPL_SIFIVE_CLINT
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imply CMD_CPU
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imply SPL_CPU
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imply SPL_OPENSBI
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imply SPL_LOAD_FIT
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imply SMP
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imply CLK_SIFIVE
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imply CLK_SIFIVE_FU540_PRCI
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imply SIFIVE_SERIAL
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imply MACB
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imply MII
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imply SPI
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imply SPI_SIFIVE
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imply MMC
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imply MMC_SPI
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imply MMC_BROKEN_CD
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imply CMD_MMC
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imply DM_GPIO
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imply SIFIVE_GPIO
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imply CMD_GPIO
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imply MISC
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imply SIFIVE_OTP
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imply DM_PWM
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imply PWM_SIFIVE
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imply DM_I2C
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imply SYS_I2C_OCORES
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if ENV_IS_IN_SPI_FLASH
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config ENV_OFFSET
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default 0x505000
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config ENV_SIZE
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default 0x20000
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config ENV_SECT_SIZE
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default 0x10000
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endif # ENV_IS_IN_SPI_FLASH
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