mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-12 22:26:16 +09:00
8ca78f2c89
Previously boards used a variety of indentations, newline styles, and
colon styles for the PCI information that is printed on bootup. This
patch unifies the style to look like:
...
NAND: 1024 MiB
PCIE1: connected as Root Complex
Scanning PCI bus 01
04 01 8086 1010 0200 00
04 01 8086 1010 0200 00
03 00 10b5 8112 0604 00
02 01 10b5 8518 0604 00
02 02 10b5 8518 0604 00
08 00 1957 0040 0b20 00
07 00 10b5 8518 0604 00
09 00 10b5 8112 0604 00
07 01 10b5 8518 0604 00
07 02 10b5 8518 0604 00
06 00 10b5 8518 0604 00
02 03 10b5 8518 0604 00
01 00 10b5 8518 0604 00
PCIE1: Bus 00 - 0b
PCIE2: connected as Root Complex
Scanning PCI bus 0d
0d 00 1957 0040 0b20 00
PCIE2: Bus 0c - 0d
In: serial
...
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
CC: wd@denx.de
CC: sr@denx.de
CC: galak@kernel.crashing.org
345 lines
8.3 KiB
C
345 lines
8.3 KiB
C
/*
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* Copyright 2007 Wind River Systemes, Inc. <www.windriver.com>
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* Copyright 2007 Embedded Specialties, Inc.
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* Joe Hamman joe.hamman@embeddedspecialties.com
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*
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* Copyright 2004 Freescale Semiconductor.
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* Jeff Brown
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* Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
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*
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* (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <command.h>
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#include <pci.h>
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#include <asm/processor.h>
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#include <asm/immap_86xx.h>
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#include <asm/fsl_pci.h>
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#include <asm/fsl_ddr_sdram.h>
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#include <libfdt.h>
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#include <fdt_support.h>
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long int fixed_sdram (void);
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int board_early_init_f (void)
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{
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return 0;
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}
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int checkboard (void)
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{
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puts ("Board: Wind River SBC8641D\n");
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return 0;
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}
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phys_size_t initdram (int board_type)
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{
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long dram_size = 0;
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#if defined(CONFIG_SPD_EEPROM)
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dram_size = fsl_ddr_sdram();
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#else
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dram_size = fixed_sdram ();
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#endif
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puts (" DDR: ");
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return dram_size;
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}
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#if defined(CONFIG_SYS_DRAM_TEST)
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int testdram (void)
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{
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uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
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uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
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uint *p;
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puts ("SDRAM test phase 1:\n");
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for (p = pstart; p < pend; p++)
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*p = 0xaaaaaaaa;
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for (p = pstart; p < pend; p++) {
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if (*p != 0xaaaaaaaa) {
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printf ("SDRAM test fails at: %08x\n", (uint) p);
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return 1;
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}
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}
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puts ("SDRAM test phase 2:\n");
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for (p = pstart; p < pend; p++)
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*p = 0x55555555;
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for (p = pstart; p < pend; p++) {
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if (*p != 0x55555555) {
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printf ("SDRAM test fails at: %08x\n", (uint) p);
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return 1;
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}
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}
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puts ("SDRAM test passed.\n");
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return 0;
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}
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#endif
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#if !defined(CONFIG_SPD_EEPROM)
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/*
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* Fixed sdram init -- doesn't use serial presence detect.
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*/
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long int fixed_sdram (void)
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{
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#if !defined(CONFIG_SYS_RAMBOOT)
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volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
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volatile ccsr_ddr_t *ddr = &immap->im_ddr1;
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ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
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ddr->cs1_bnds = CONFIG_SYS_DDR_CS1_BNDS;
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ddr->cs2_bnds = CONFIG_SYS_DDR_CS2_BNDS;
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ddr->cs3_bnds = CONFIG_SYS_DDR_CS3_BNDS;
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ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
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ddr->cs1_config = CONFIG_SYS_DDR_CS1_CONFIG;
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ddr->cs2_config = CONFIG_SYS_DDR_CS2_CONFIG;
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ddr->cs3_config = CONFIG_SYS_DDR_CS3_CONFIG;
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ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
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ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
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ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
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ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
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ddr->sdram_cfg = CONFIG_SYS_DDR_CFG_1A;
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ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CFG_2;
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ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
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ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
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ddr->sdram_mode_cntl = CONFIG_SYS_DDR_MODE_CTL;
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ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
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ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
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ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
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asm ("sync;isync");
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udelay (500);
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ddr->sdram_cfg = CONFIG_SYS_DDR_CFG_1B;
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asm ("sync; isync");
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udelay (500);
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ddr = &immap->im_ddr2;
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ddr->cs0_bnds = CONFIG_SYS_DDR2_CS0_BNDS;
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ddr->cs1_bnds = CONFIG_SYS_DDR2_CS1_BNDS;
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ddr->cs2_bnds = CONFIG_SYS_DDR2_CS2_BNDS;
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ddr->cs3_bnds = CONFIG_SYS_DDR2_CS3_BNDS;
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ddr->cs0_config = CONFIG_SYS_DDR2_CS0_CONFIG;
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ddr->cs1_config = CONFIG_SYS_DDR2_CS1_CONFIG;
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ddr->cs2_config = CONFIG_SYS_DDR2_CS2_CONFIG;
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ddr->cs3_config = CONFIG_SYS_DDR2_CS3_CONFIG;
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ddr->timing_cfg_3 = CONFIG_SYS_DDR2_EXT_REFRESH;
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ddr->timing_cfg_0 = CONFIG_SYS_DDR2_TIMING_0;
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ddr->timing_cfg_1 = CONFIG_SYS_DDR2_TIMING_1;
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ddr->timing_cfg_2 = CONFIG_SYS_DDR2_TIMING_2;
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ddr->sdram_cfg = CONFIG_SYS_DDR2_CFG_1A;
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ddr->sdram_cfg_2 = CONFIG_SYS_DDR2_CFG_2;
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ddr->sdram_mode = CONFIG_SYS_DDR2_MODE_1;
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ddr->sdram_mode_2 = CONFIG_SYS_DDR2_MODE_2;
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ddr->sdram_mode_cntl = CONFIG_SYS_DDR2_MODE_CTL;
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ddr->sdram_interval = CONFIG_SYS_DDR2_INTERVAL;
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ddr->sdram_data_init = CONFIG_SYS_DDR2_DATA_INIT;
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ddr->sdram_clk_cntl = CONFIG_SYS_DDR2_CLK_CTRL;
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asm ("sync;isync");
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udelay (500);
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ddr->sdram_cfg = CONFIG_SYS_DDR2_CFG_1B;
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asm ("sync; isync");
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udelay (500);
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#endif
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return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
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}
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#endif /* !defined(CONFIG_SPD_EEPROM) */
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#if defined(CONFIG_PCI)
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/*
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* Initialize PCI Devices, report devices found.
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*/
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#ifndef CONFIG_PCI_PNP
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static struct pci_config_table pci_fsl86xxads_config_table[] = {
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{PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
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PCI_IDSEL_NUMBER, PCI_ANY_ID,
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pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
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PCI_ENET0_MEMADDR,
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PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER}},
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{}
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};
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#endif
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static struct pci_controller pcie1_hose = {
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#ifndef CONFIG_PCI_PNP
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config_table:pci_mpc86xxcts_config_table
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#endif
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};
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#endif /* CONFIG_PCI */
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#ifdef CONFIG_PCIE2
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static struct pci_controller pcie2_hose;
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#endif /* CONFIG_PCIE2 */
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int first_free_busno = 0;
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void pci_init_board(void)
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{
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struct fsl_pci_info pci_info[2];
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volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR;
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volatile ccsr_gur_t *gur = &immap->im_gur;
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uint devdisr = in_be32(&gur->devdisr);
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uint io_sel = (gur->pordevsr & MPC8641_PORDEVSR_IO_SEL)
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>> MPC8641_PORDEVSR_IO_SEL_SHIFT;
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int pcie_ep;
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int num = 0;
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#ifdef CONFIG_PCIE1
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int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel);
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if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIEX1)) {
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SET_STD_PCIE_INFO(pci_info[num], 1);
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pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
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printf("PCIE1: connected as %s (base addr %lx)\n",
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pcie_ep ? "Endpoint" : "Root Complex",
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pci_info[num].regs);
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first_free_busno = fsl_pci_init_port(&pci_info[num++],
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&pcie1_hose, first_free_busno);
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} else {
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puts("PCIE1: disabled\n");
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}
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#else
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puts("PCIE1: disabled\n");
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#endif /* CONFIG_PCIE1 */
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#ifdef CONFIG_PCIE2
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SET_STD_PCIE_INFO(pci_info[num], 2);
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pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs);
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printf("PCIE2: connected as %s (base addr %lx)\n",
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pcie_ep ? "Endpoint" : "Root Complex",
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pci_info[num].regs);
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first_free_busno = fsl_pci_init_port(&pci_info[num++],
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&pcie2_hose, first_free_busno);
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#else
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puts("PCIE2: disabled\n");
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#endif /* CONFIG_PCIE2 */
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}
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#if defined(CONFIG_OF_BOARD_SETUP)
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void ft_board_setup (void *blob, bd_t *bd)
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{
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ft_cpu_setup(blob, bd);
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FT_FSL_PCI_SETUP;
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}
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#endif
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void sbc8641d_reset_board (void)
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{
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puts ("Resetting board....\n");
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}
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/*
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* get_board_sys_clk
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* Clock is fixed at 1GHz on this board. Used for CONFIG_SYS_CLK_FREQ
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*/
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unsigned long get_board_sys_clk (ulong dummy)
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{
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int i;
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ulong val = 0;
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i = 5;
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i &= 0x07;
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switch (i) {
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case 0:
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val = 33000000;
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break;
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case 1:
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val = 40000000;
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break;
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case 2:
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val = 50000000;
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break;
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case 3:
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val = 66000000;
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break;
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case 4:
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val = 83000000;
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break;
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case 5:
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val = 100000000;
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break;
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case 6:
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val = 134000000;
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break;
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case 7:
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val = 166000000;
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break;
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}
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return val;
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}
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void board_reset(void)
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{
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#ifdef CONFIG_SYS_RESET_ADDRESS
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ulong addr = CONFIG_SYS_RESET_ADDRESS;
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/* flush and disable I/D cache */
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__asm__ __volatile__ ("mfspr 3, 1008" ::: "r3");
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__asm__ __volatile__ ("ori 5, 5, 0xcc00" ::: "r5");
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__asm__ __volatile__ ("ori 4, 3, 0xc00" ::: "r4");
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__asm__ __volatile__ ("andc 5, 3, 5" ::: "r5");
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__asm__ __volatile__ ("sync");
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__asm__ __volatile__ ("mtspr 1008, 4");
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__asm__ __volatile__ ("isync");
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__asm__ __volatile__ ("sync");
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__asm__ __volatile__ ("mtspr 1008, 5");
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__asm__ __volatile__ ("isync");
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__asm__ __volatile__ ("sync");
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/*
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* SRR0 has system reset vector, SRR1 has default MSR value
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* rfi restores MSR from SRR1 and sets the PC to the SRR0 value
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*/
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__asm__ __volatile__ ("mtspr 26, %0" :: "r" (addr));
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__asm__ __volatile__ ("li 4, (1 << 6)" ::: "r4");
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__asm__ __volatile__ ("mtspr 27, 4");
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__asm__ __volatile__ ("rfi");
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#endif
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}
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#ifdef CONFIG_MP
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extern void cpu_mp_lmb_reserve(struct lmb *lmb);
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void board_lmb_reserve(struct lmb *lmb)
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{
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cpu_mp_lmb_reserve(lmb);
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}
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#endif
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