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https://github.com/brain-hackers/u-boot-brain
synced 2024-08-22 01:48:52 +09:00
![Peter Tyser](/assets/img/avatar_default.png)
Previously boards used a variety of indentations, newline styles, and colon styles for the PCI information that is printed on bootup. This patch unifies the style to look like: ... NAND: 1024 MiB PCIE1: connected as Root Complex Scanning PCI bus 01 04 01 8086 1010 0200 00 04 01 8086 1010 0200 00 03 00 10b5 8112 0604 00 02 01 10b5 8518 0604 00 02 02 10b5 8518 0604 00 08 00 1957 0040 0b20 00 07 00 10b5 8518 0604 00 09 00 10b5 8112 0604 00 07 01 10b5 8518 0604 00 07 02 10b5 8518 0604 00 06 00 10b5 8518 0604 00 02 03 10b5 8518 0604 00 01 00 10b5 8518 0604 00 PCIE1: Bus 00 - 0b PCIE2: connected as Root Complex Scanning PCI bus 0d 0d 00 1957 0040 0b20 00 PCIE2: Bus 0c - 0d In: serial ... Signed-off-by: Peter Tyser <ptyser@xes-inc.com> CC: wd@denx.de CC: sr@denx.de CC: galak@kernel.crashing.org
671 lines
19 KiB
C
671 lines
19 KiB
C
/*
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* Copyright 2009-2010 Freescale Semiconductor.
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*
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* (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <hwconfig.h>
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#include <pci.h>
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#include <asm/processor.h>
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#include <asm/mmu.h>
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#include <asm/cache.h>
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#include <asm/immap_85xx.h>
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#include <asm/fsl_pci.h>
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#include <asm/fsl_ddr_sdram.h>
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#include <asm/io.h>
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#include <spd_sdram.h>
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#include <i2c.h>
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#include <ioports.h>
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#include <libfdt.h>
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#include <fdt_support.h>
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#include <fsl_esdhc.h>
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#include "bcsr.h"
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#if defined(CONFIG_PQ_MDS_PIB)
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#include "../common/pq-mds-pib.h"
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#endif
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phys_size_t fixed_sdram(void);
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const qe_iop_conf_t qe_iop_conf_tab[] = {
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/* QE_MUX_MDC */
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{2, 31, 1, 0, 1}, /* QE_MUX_MDC */
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/* QE_MUX_MDIO */
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{2, 30, 3, 0, 2}, /* QE_MUX_MDIO */
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#if defined(CONFIG_SYS_UCC_RGMII_MODE)
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/* UCC_1_RGMII */
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{2, 11, 2, 0, 1}, /* CLK12 */
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{0, 0, 1, 0, 3}, /* ENET1_TXD0_SER1_TXD0 */
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{0, 1, 1, 0, 3}, /* ENET1_TXD1_SER1_TXD1 */
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{0, 2, 1, 0, 1}, /* ENET1_TXD2_SER1_TXD2 */
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{0, 3, 1, 0, 2}, /* ENET1_TXD3_SER1_TXD3 */
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{0, 6, 2, 0, 3}, /* ENET1_RXD0_SER1_RXD0 */
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{0, 7, 2, 0, 1}, /* ENET1_RXD1_SER1_RXD1 */
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{0, 8, 2, 0, 2}, /* ENET1_RXD2_SER1_RXD2 */
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{0, 9, 2, 0, 2}, /* ENET1_RXD3_SER1_RXD3 */
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{0, 4, 1, 0, 2}, /* ENET1_TX_EN_SER1_RTS_B */
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{0, 12, 2, 0, 3}, /* ENET1_RX_DV_SER1_CTS_B */
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{2, 8, 2, 0, 1}, /* ENET1_GRXCLK */
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{2, 20, 1, 0, 2}, /* ENET1_GTXCLK */
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/* UCC_2_RGMII */
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{2, 16, 2, 0, 3}, /* CLK17 */
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{0, 14, 1, 0, 2}, /* ENET2_TXD0_SER2_TXD0 */
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{0, 15, 1, 0, 2}, /* ENET2_TXD1_SER2_TXD1 */
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{0, 16, 1, 0, 1}, /* ENET2_TXD2_SER2_TXD2 */
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{0, 17, 1, 0, 1}, /* ENET2_TXD3_SER2_TXD3 */
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{0, 20, 2, 0, 2}, /* ENET2_RXD0_SER2_RXD0 */
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{0, 21, 2, 0, 1}, /* ENET2_RXD1_SER2_RXD1 */
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{0, 22, 2, 0, 1}, /* ENET2_RXD2_SER2_RXD2 */
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{0, 23, 2, 0, 1}, /* ENET2_RXD3_SER2_RXD3 */
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{0, 18, 1, 0, 2}, /* ENET2_TX_EN_SER2_RTS_B */
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{0, 26, 2, 0, 3}, /* ENET2_RX_DV_SER2_CTS_B */
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{2, 3, 2, 0, 1}, /* ENET2_GRXCLK */
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{2, 2, 1, 0, 2}, /* ENET2_GTXCLK */
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/* UCC_3_RGMII */
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{2, 11, 2, 0, 1}, /* CLK12 */
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{0, 29, 1, 0, 2}, /* ENET3_TXD0_SER3_TXD0 */
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{0, 30, 1, 0, 3}, /* ENET3_TXD1_SER3_TXD1 */
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{0, 31, 1, 0, 2}, /* ENET3_TXD2_SER3_TXD2 */
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{1, 0, 1, 0, 3}, /* ENET3_TXD3_SER3_TXD3 */
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{1, 3, 2, 0, 3}, /* ENET3_RXD0_SER3_RXD0 */
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{1, 4, 2, 0, 1}, /* ENET3_RXD1_SER3_RXD1 */
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{1, 5, 2, 0, 2}, /* ENET3_RXD2_SER3_RXD2 */
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{1, 6, 2, 0, 3}, /* ENET3_RXD3_SER3_RXD3 */
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{1, 1, 1, 0, 1}, /* ENET3_TX_EN_SER3_RTS_B */
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{1, 9, 2, 0, 3}, /* ENET3_RX_DV_SER3_CTS_B */
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{2, 9, 2, 0, 2}, /* ENET3_GRXCLK */
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{2, 25, 1, 0, 2}, /* ENET3_GTXCLK */
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/* UCC_4_RGMII */
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{2, 16, 2, 0, 3}, /* CLK17 */
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{1, 12, 1, 0, 2}, /* ENET4_TXD0_SER4_TXD0 */
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{1, 13, 1, 0, 2}, /* ENET4_TXD1_SER4_TXD1 */
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{1, 14, 1, 0, 1}, /* ENET4_TXD2_SER4_TXD2 */
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{1, 15, 1, 0, 2}, /* ENET4_TXD3_SER4_TXD3 */
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{1, 18, 2, 0, 2}, /* ENET4_RXD0_SER4_RXD0 */
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{1, 19, 2, 0, 1}, /* ENET4_RXD1_SER4_RXD1 */
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{1, 20, 2, 0, 1}, /* ENET4_RXD2_SER4_RXD2 */
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{1, 21, 2, 0, 2}, /* ENET4_RXD3_SER4_RXD3 */
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{1, 16, 1, 0, 2}, /* ENET4_TX_EN_SER4_RTS_B */
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{1, 24, 2, 0, 3}, /* ENET4_RX_DV_SER4_CTS_B */
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{2, 17, 2, 0, 2}, /* ENET4_GRXCLK */
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{2, 24, 1, 0, 2}, /* ENET4_GTXCLK */
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#elif defined(CONFIG_SYS_UCC_RMII_MODE)
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/* UCC_1_RMII */
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{2, 15, 2, 0, 1}, /* CLK16 */
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{0, 0, 1, 0, 3}, /* ENET1_TXD0_SER1_TXD0 */
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{0, 1, 1, 0, 3}, /* ENET1_TXD1_SER1_TXD1 */
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{0, 6, 2, 0, 3}, /* ENET1_RXD0_SER1_RXD0 */
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{0, 7, 2, 0, 1}, /* ENET1_RXD1_SER1_RXD1 */
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{0, 4, 1, 0, 2}, /* ENET1_TX_EN_SER1_RTS_B */
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{0, 12, 2, 0, 3}, /* ENET1_RX_DV_SER1_CTS_B */
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/* UCC_2_RMII */
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{2, 15, 2, 0, 1}, /* CLK16 */
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{0, 14, 1, 0, 2}, /* ENET2_TXD0_SER2_TXD0 */
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{0, 15, 1, 0, 2}, /* ENET2_TXD1_SER2_TXD1 */
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{0, 20, 2, 0, 2}, /* ENET2_RXD0_SER2_RXD0 */
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{0, 21, 2, 0, 1}, /* ENET2_RXD1_SER2_RXD1 */
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{0, 18, 1, 0, 2}, /* ENET2_TX_EN_SER2_RTS_B */
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{0, 26, 2, 0, 3}, /* ENET2_RX_DV_SER2_CTS_B */
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/* UCC_3_RMII */
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{2, 15, 2, 0, 1}, /* CLK16 */
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{0, 29, 1, 0, 2}, /* ENET3_TXD0_SER3_TXD0 */
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{0, 30, 1, 0, 3}, /* ENET3_TXD1_SER3_TXD1 */
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{1, 3, 2, 0, 3}, /* ENET3_RXD0_SER3_RXD0 */
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{1, 4, 2, 0, 1}, /* ENET3_RXD1_SER3_RXD1 */
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{1, 1, 1, 0, 1}, /* ENET3_TX_EN_SER3_RTS_B */
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{1, 9, 2, 0, 3}, /* ENET3_RX_DV_SER3_CTS_B */
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/* UCC_4_RMII */
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{2, 15, 2, 0, 1}, /* CLK16 */
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{1, 12, 1, 0, 2}, /* ENET4_TXD0_SER4_TXD0 */
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{1, 13, 1, 0, 2}, /* ENET4_TXD1_SER4_TXD1 */
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{1, 18, 2, 0, 2}, /* ENET4_RXD0_SER4_RXD0 */
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{1, 19, 2, 0, 1}, /* ENET4_RXD1_SER4_RXD1 */
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{1, 16, 1, 0, 2}, /* ENET4_TX_EN_SER4_RTS_B */
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{1, 24, 2, 0, 3}, /* ENET4_RX_DV_SER4_CTS_B */
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#endif
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/* UART1 is muxed with QE PortF bit [9-12].*/
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{5, 12, 2, 0, 3}, /* UART1_SIN */
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{5, 9, 1, 0, 3}, /* UART1_SOUT */
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{5, 10, 2, 0, 3}, /* UART1_CTS_B */
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{5, 11, 1, 0, 2}, /* UART1_RTS_B */
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/* QE UART */
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{0, 19, 1, 0, 2}, /* QEUART_TX */
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{1, 17, 2, 0, 3}, /* QEUART_RX */
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{0, 25, 1, 0, 1}, /* QEUART_RTS */
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{1, 23, 2, 0, 1}, /* QEUART_CTS */
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/* QE USB */
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{5, 3, 1, 0, 1}, /* USB_OE */
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{5, 4, 1, 0, 2}, /* USB_TP */
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{5, 5, 1, 0, 2}, /* USB_TN */
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{5, 6, 2, 0, 2}, /* USB_RP */
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{5, 7, 2, 0, 1}, /* USB_RX */
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{5, 8, 2, 0, 1}, /* USB_RN */
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{2, 4, 2, 0, 2}, /* CLK5 */
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/* SPI Flash, M25P40 */
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{4, 27, 3, 0, 1}, /* SPI_MOSI */
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{4, 28, 3, 0, 1}, /* SPI_MISO */
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{4, 29, 3, 0, 1}, /* SPI_CLK */
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{4, 30, 1, 0, 0}, /* SPI_SEL, GPIO */
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{0, 0, 0, 0, QE_IOP_TAB_END} /* END of table */
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};
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void local_bus_init(void);
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int board_early_init_f (void)
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{
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/*
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* Initialize local bus.
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*/
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local_bus_init ();
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enable_8569mds_flash_write();
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#ifdef CONFIG_QE
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enable_8569mds_qe_uec();
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#endif
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#if CONFIG_SYS_I2C2_OFFSET
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/* Enable I2C2 signals instead of SD signals */
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volatile struct ccsr_gur *gur;
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gur = (struct ccsr_gur *)(CONFIG_SYS_IMMR + 0xe0000);
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gur->plppar1 &= ~PLPPAR1_I2C_BIT_MASK;
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gur->plppar1 |= PLPPAR1_I2C2_VAL;
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gur->plpdir1 &= ~PLPDIR1_I2C_BIT_MASK;
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gur->plpdir1 |= PLPDIR1_I2C2_VAL;
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disable_8569mds_brd_eeprom_write_protect();
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#endif
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return 0;
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}
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int board_early_init_r(void)
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{
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const unsigned int flashbase = CONFIG_SYS_NAND_BASE;
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const u8 flash_esel = 0;
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/*
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* Remap Boot flash to caching-inhibited
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* so that flash can be erased properly.
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*/
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/* Flush d-cache and invalidate i-cache of any FLASH data */
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flush_dcache();
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invalidate_icache();
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/* invalidate existing TLB entry for flash */
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disable_tlb(flash_esel);
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set_tlb(1, flashbase, CONFIG_SYS_NAND_BASE, /* tlb, epn, rpn */
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */
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0, flash_esel, /* ts, esel */
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BOOKE_PAGESZ_64M, 1); /* tsize, iprot */
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return 0;
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}
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int checkboard (void)
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{
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printf ("Board: 8569 MDS\n");
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return 0;
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}
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phys_size_t
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initdram(int board_type)
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{
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long dram_size = 0;
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puts("Initializing\n");
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#if defined(CONFIG_DDR_DLL)
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/*
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* Work around to stabilize DDR DLL MSYNC_IN.
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* Errata DDR9 seems to have been fixed.
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* This is now the workaround for Errata DDR11:
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* Override DLL = 1, Course Adj = 1, Tap Select = 0
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*/
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volatile ccsr_gur_t *gur =
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(void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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out_be32(&gur->ddrdllcr, 0x81000000);
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udelay(200);
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#endif
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#ifdef CONFIG_SPD_EEPROM
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dram_size = fsl_ddr_sdram();
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#else
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dram_size = fixed_sdram();
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#endif
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dram_size = setup_ddr_tlbs(dram_size / 0x100000);
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dram_size *= 0x100000;
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puts(" DDR: ");
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return dram_size;
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}
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#if !defined(CONFIG_SPD_EEPROM)
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phys_size_t fixed_sdram(void)
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{
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volatile ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC85xx_DDR_ADDR;
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uint d_init;
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out_be32(&ddr->cs0_bnds, CONFIG_SYS_DDR_CS0_BNDS);
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out_be32(&ddr->cs0_config, CONFIG_SYS_DDR_CS0_CONFIG);
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out_be32(&ddr->timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
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out_be32(&ddr->timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
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out_be32(&ddr->timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
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out_be32(&ddr->timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
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out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG);
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out_be32(&ddr->sdram_cfg_2, CONFIG_SYS_DDR_SDRAM_CFG_2);
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out_be32(&ddr->sdram_mode, CONFIG_SYS_DDR_SDRAM_MODE);
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out_be32(&ddr->sdram_mode_2, CONFIG_SYS_DDR_SDRAM_MODE_2);
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out_be32(&ddr->sdram_interval, CONFIG_SYS_DDR_SDRAM_INTERVAL);
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out_be32(&ddr->sdram_data_init, CONFIG_SYS_DDR_DATA_INIT);
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out_be32(&ddr->sdram_clk_cntl, CONFIG_SYS_DDR_SDRAM_CLK_CNTL);
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out_be32(&ddr->timing_cfg_4, CONFIG_SYS_DDR_TIMING_4);
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out_be32(&ddr->timing_cfg_5, CONFIG_SYS_DDR_TIMING_5);
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out_be32(&ddr->ddr_zq_cntl, CONFIG_SYS_DDR_ZQ_CNTL);
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out_be32(&ddr->ddr_wrlvl_cntl, CONFIG_SYS_DDR_WRLVL_CNTL);
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out_be32(&ddr->sdram_cfg_2, CONFIG_SYS_DDR_SDRAM_CFG_2);
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#if defined (CONFIG_DDR_ECC)
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out_be32(&ddr->err_int_en, CONFIG_SYS_DDR_ERR_INT_EN);
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out_be32(&ddr->err_disable, CONFIG_SYS_DDR_ERR_DIS);
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out_be32(&ddr->err_sbe, CONFIG_SYS_DDR_SBE);
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#endif
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udelay(500);
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out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL);
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#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
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d_init = 1;
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debug("DDR - 1st controller: memory initializing\n");
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/*
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* Poll until memory is initialized.
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* 512 Meg at 400 might hit this 200 times or so.
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*/
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while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) {
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udelay(1000);
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}
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debug("DDR: memory initialized\n\n");
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udelay(500);
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#endif
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return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
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}
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#endif
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/*
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* Initialize Local Bus
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*/
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void
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local_bus_init(void)
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{
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volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
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uint clkdiv;
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uint lbc_hz;
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sys_info_t sysinfo;
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get_sys_info(&sysinfo);
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clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2;
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lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
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out_be32(&gur->lbiuiplldcr1, 0x00078080);
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if (clkdiv == 16)
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out_be32(&gur->lbiuiplldcr0, 0x7c0f1bf0);
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else if (clkdiv == 8)
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out_be32(&gur->lbiuiplldcr0, 0x6c0f1bf0);
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else if (clkdiv == 4)
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out_be32(&gur->lbiuiplldcr0, 0x5c0f1bf0);
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out_be32(&lbc->lcrr, (u32)in_be32(&lbc->lcrr)| 0x00030000);
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}
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static void fdt_board_disable_serial(void *blob, bd_t *bd, const char *alias)
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{
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const char *status = "disabled";
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int off;
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int err;
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off = fdt_path_offset(blob, alias);
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if (off < 0) {
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printf("WARNING: could not find %s alias: %s.\n", alias,
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fdt_strerror(off));
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return;
|
|
}
|
|
|
|
err = fdt_setprop(blob, off, "status", status, strlen(status) + 1);
|
|
if (err) {
|
|
printf("WARNING: could not set status for serial0: %s.\n",
|
|
fdt_strerror(err));
|
|
return;
|
|
}
|
|
}
|
|
|
|
/*
|
|
* Because of an erratum in prototype boards it is impossible to use eSDHC
|
|
* without disabling UART0 (which makes it quite easy to 'brick' the board
|
|
* by simply issung 'setenv hwconfig esdhc', and not able to interact with
|
|
* U-Boot anylonger).
|
|
*
|
|
* So, but default we assume that the board is a prototype, which is a most
|
|
* safe assumption. There is no way to determine board revision from a
|
|
* register, so we use hwconfig.
|
|
*/
|
|
|
|
static int prototype_board(void)
|
|
{
|
|
if (hwconfig_subarg("board", "rev", NULL))
|
|
return hwconfig_subarg_cmp("board", "rev", "prototype");
|
|
return 1;
|
|
}
|
|
|
|
static int esdhc_disables_uart0(void)
|
|
{
|
|
return prototype_board() ||
|
|
hwconfig_subarg_cmp("esdhc", "mode", "4-bits");
|
|
}
|
|
|
|
static void fdt_board_fixup_qe_uart(void *blob, bd_t *bd)
|
|
{
|
|
u8 *bcsr = (u8 *)CONFIG_SYS_BCSR_BASE;
|
|
const char *devtype = "serial";
|
|
const char *compat = "ucc_uart";
|
|
const char *clk = "brg9";
|
|
u32 portnum = 0;
|
|
int off = -1;
|
|
|
|
if (!hwconfig("qe_uart"))
|
|
return;
|
|
|
|
if (hwconfig("esdhc") && esdhc_disables_uart0()) {
|
|
printf("QE UART: won't enable with esdhc.\n");
|
|
return;
|
|
}
|
|
|
|
fdt_board_disable_serial(blob, bd, "serial1");
|
|
|
|
while (1) {
|
|
const u32 *idx;
|
|
int len;
|
|
|
|
off = fdt_node_offset_by_compatible(blob, off, "ucc_geth");
|
|
if (off < 0) {
|
|
printf("WARNING: unable to fixup device tree for "
|
|
"QE UART\n");
|
|
return;
|
|
}
|
|
|
|
idx = fdt_getprop(blob, off, "cell-index", &len);
|
|
if (!idx || len != sizeof(*idx) || *idx != fdt32_to_cpu(2))
|
|
continue;
|
|
break;
|
|
}
|
|
|
|
fdt_setprop(blob, off, "device_type", devtype, strlen(devtype) + 1);
|
|
fdt_setprop(blob, off, "compatible", compat, strlen(compat) + 1);
|
|
fdt_setprop(blob, off, "tx-clock-name", clk, strlen(clk) + 1);
|
|
fdt_setprop(blob, off, "rx-clock-name", clk, strlen(clk) + 1);
|
|
fdt_setprop(blob, off, "port-number", &portnum, sizeof(portnum));
|
|
|
|
setbits_8(&bcsr[15], BCSR15_QEUART_EN);
|
|
}
|
|
|
|
#ifdef CONFIG_FSL_ESDHC
|
|
|
|
int board_mmc_init(bd_t *bd)
|
|
{
|
|
struct ccsr_gur *gur = (struct ccsr_gur *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
|
|
u8 *bcsr = (u8 *)CONFIG_SYS_BCSR_BASE;
|
|
u8 bcsr6 = BCSR6_SD_CARD_1BIT;
|
|
|
|
if (!hwconfig("esdhc"))
|
|
return 0;
|
|
|
|
printf("Enabling eSDHC...\n"
|
|
" For eSDHC to function, I2C2 ");
|
|
if (esdhc_disables_uart0()) {
|
|
printf("and UART0 should be disabled.\n");
|
|
printf(" Redirecting stderr, stdout and stdin to UART1...\n");
|
|
console_assign(stderr, "eserial1");
|
|
console_assign(stdout, "eserial1");
|
|
console_assign(stdin, "eserial1");
|
|
printf("Switched to UART1 (initial log has been printed to "
|
|
"UART0).\n");
|
|
|
|
clrsetbits_be32(&gur->plppar1, PLPPAR1_UART0_BIT_MASK,
|
|
PLPPAR1_ESDHC_4BITS_VAL);
|
|
clrsetbits_be32(&gur->plpdir1, PLPDIR1_UART0_BIT_MASK,
|
|
PLPDIR1_ESDHC_4BITS_VAL);
|
|
bcsr6 |= BCSR6_SD_CARD_4BITS;
|
|
} else {
|
|
printf("should be disabled.\n");
|
|
}
|
|
|
|
/* Assign I2C2 signals to eSDHC. */
|
|
clrsetbits_be32(&gur->plppar1, PLPPAR1_I2C_BIT_MASK,
|
|
PLPPAR1_ESDHC_VAL);
|
|
clrsetbits_be32(&gur->plpdir1, PLPDIR1_I2C_BIT_MASK,
|
|
PLPDIR1_ESDHC_VAL);
|
|
|
|
/* Mux I2C2 (and optionally UART0) signals to eSDHC. */
|
|
setbits_8(&bcsr[6], bcsr6);
|
|
|
|
return fsl_esdhc_mmc_init(bd);
|
|
}
|
|
|
|
static void fdt_board_fixup_esdhc(void *blob, bd_t *bd)
|
|
{
|
|
const char *status = "disabled";
|
|
int off = -1;
|
|
|
|
if (!hwconfig("esdhc"))
|
|
return;
|
|
|
|
if (esdhc_disables_uart0())
|
|
fdt_board_disable_serial(blob, bd, "serial0");
|
|
|
|
while (1) {
|
|
const u32 *idx;
|
|
int len;
|
|
|
|
off = fdt_node_offset_by_compatible(blob, off, "fsl-i2c");
|
|
if (off < 0)
|
|
break;
|
|
|
|
idx = fdt_getprop(blob, off, "cell-index", &len);
|
|
if (!idx || len != sizeof(*idx))
|
|
continue;
|
|
|
|
if (*idx == 1) {
|
|
fdt_setprop(blob, off, "status", status,
|
|
strlen(status) + 1);
|
|
break;
|
|
}
|
|
}
|
|
|
|
if (hwconfig_subarg_cmp("esdhc", "mode", "4-bits")) {
|
|
off = fdt_node_offset_by_compatible(blob, -1, "fsl,esdhc");
|
|
if (off < 0) {
|
|
printf("WARNING: could not find esdhc node\n");
|
|
return;
|
|
}
|
|
fdt_delprop(blob, off, "sdhci,1-bit-only");
|
|
}
|
|
}
|
|
#else
|
|
static inline void fdt_board_fixup_esdhc(void *blob, bd_t *bd) {}
|
|
#endif
|
|
|
|
static void fdt_board_fixup_qe_usb(void *blob, bd_t *bd)
|
|
{
|
|
u8 *bcsr = (u8 *)CONFIG_SYS_BCSR_BASE;
|
|
|
|
if (hwconfig_subarg_cmp("qe_usb", "speed", "low"))
|
|
clrbits_8(&bcsr[17], BCSR17_nUSBLOWSPD);
|
|
else
|
|
setbits_8(&bcsr[17], BCSR17_nUSBLOWSPD);
|
|
|
|
if (hwconfig_subarg_cmp("qe_usb", "mode", "peripheral")) {
|
|
clrbits_8(&bcsr[17], BCSR17_USBVCC);
|
|
clrbits_8(&bcsr[17], BCSR17_USBMODE);
|
|
do_fixup_by_compat(blob, "fsl,mpc8569-qe-usb", "mode",
|
|
"peripheral", sizeof("peripheral"), 1);
|
|
} else {
|
|
setbits_8(&bcsr[17], BCSR17_USBVCC);
|
|
setbits_8(&bcsr[17], BCSR17_USBMODE);
|
|
}
|
|
|
|
clrbits_8(&bcsr[17], BCSR17_nUSBEN);
|
|
}
|
|
|
|
#ifdef CONFIG_PCIE1
|
|
static struct pci_controller pcie1_hose;
|
|
#endif /* CONFIG_PCIE1 */
|
|
|
|
#ifdef CONFIG_PCI
|
|
void pci_init_board(void)
|
|
{
|
|
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
|
|
struct fsl_pci_info pci_info[1];
|
|
u32 devdisr, pordevsr, io_sel;
|
|
int first_free_busno = 0;
|
|
int num = 0;
|
|
|
|
int pcie_ep, pcie_configured;
|
|
|
|
devdisr = in_be32(&gur->devdisr);
|
|
pordevsr = in_be32(&gur->pordevsr);
|
|
io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
|
|
|
|
debug (" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel);
|
|
|
|
#if defined(CONFIG_PQ_MDS_PIB)
|
|
pib_init();
|
|
#endif
|
|
|
|
#ifdef CONFIG_PCIE1
|
|
pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel);
|
|
|
|
if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
|
|
SET_STD_PCIE_INFO(pci_info[num], 1);
|
|
pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
|
|
printf("PCIE1: connected to Slot as %s (base addr %lx)\n",
|
|
pcie_ep ? "Endpoint" : "Root Complex",
|
|
pci_info[num].regs);
|
|
first_free_busno = fsl_pci_init_port(&pci_info[num++],
|
|
&pcie1_hose, first_free_busno);
|
|
} else {
|
|
printf("PCIE1: disabled\n");
|
|
}
|
|
|
|
puts("\n");
|
|
#else
|
|
setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */
|
|
#endif
|
|
|
|
}
|
|
#endif /* CONFIG_PCI */
|
|
|
|
#if defined(CONFIG_OF_BOARD_SETUP)
|
|
void ft_board_setup(void *blob, bd_t *bd)
|
|
{
|
|
#if defined(CONFIG_SYS_UCC_RMII_MODE)
|
|
int nodeoff, off, err;
|
|
unsigned int val;
|
|
const u32 *ph;
|
|
const u32 *index;
|
|
|
|
/* fixup device tree for supporting rmii mode */
|
|
nodeoff = -1;
|
|
while ((nodeoff = fdt_node_offset_by_compatible(blob, nodeoff,
|
|
"ucc_geth")) >= 0) {
|
|
err = fdt_setprop_string(blob, nodeoff, "tx-clock-name",
|
|
"clk16");
|
|
if (err < 0) {
|
|
printf("WARNING: could not set tx-clock-name %s.\n",
|
|
fdt_strerror(err));
|
|
break;
|
|
}
|
|
|
|
err = fdt_fixup_phy_connection(blob, nodeoff, RMII);
|
|
|
|
if (err < 0) {
|
|
printf("WARNING: could not set phy-connection-type "
|
|
"%s.\n", fdt_strerror(err));
|
|
break;
|
|
}
|
|
|
|
index = fdt_getprop(blob, nodeoff, "cell-index", 0);
|
|
if (index == NULL) {
|
|
printf("WARNING: could not get cell-index of ucc\n");
|
|
break;
|
|
}
|
|
|
|
ph = fdt_getprop(blob, nodeoff, "phy-handle", 0);
|
|
if (ph == NULL) {
|
|
printf("WARNING: could not get phy-handle of ucc\n");
|
|
break;
|
|
}
|
|
|
|
off = fdt_node_offset_by_phandle(blob, *ph);
|
|
if (off < 0) {
|
|
printf("WARNING: could not get phy node %s.\n",
|
|
fdt_strerror(err));
|
|
break;
|
|
}
|
|
|
|
val = 0x7 + *index; /* RMII phy address starts from 0x8 */
|
|
|
|
err = fdt_setprop(blob, off, "reg", &val, sizeof(u32));
|
|
if (err < 0) {
|
|
printf("WARNING: could not set reg for phy-handle "
|
|
"%s.\n", fdt_strerror(err));
|
|
break;
|
|
}
|
|
}
|
|
#endif
|
|
ft_cpu_setup(blob, bd);
|
|
|
|
FT_FSL_PCI_SETUP;
|
|
|
|
fdt_board_fixup_esdhc(blob, bd);
|
|
fdt_board_fixup_qe_uart(blob, bd);
|
|
fdt_board_fixup_qe_usb(blob, bd);
|
|
}
|
|
#endif
|