mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-30 22:08:52 +09:00
![Peng Fan](/assets/img/avatar_default.png)
Meet the following boot hang. " U-Boot SPL 2019.04-00661-gdc80a012e4 (Apr 25 2019 - 10:31:57 +0800) Trying to boot from MMC1 U-Boot 2019.04-00661-gdc80a012e4 (Apr 25 2019 - 10:31:57 +0800) CPU: Freescale i.MX6Q rev1.5 996 MHz (running at 792 MHz) CPU: Automotive temperature grade (-40C to 125C)Reset cause: POR Model: Freescale i.MX6 Quad SABRE Smart Device Board Board: MX6-SabreSD I2C: ready DRAM: 1 GiB Video device 'ipu@2400000' cannot allocate frame buffer memory -ensure the device is set up before relocation Error binding driver 'ipuv3_video': -28 Video device 'ipu@2800000' cannot allocate frame buffer memory -ensure the device is set up before relocation Error binding driver 'ipuv3_video': -28 Some drivers failed to bind Error binding driver 'generic_simple_bus': -28 Some drivers failed to bind initcall sequence 4ffe4500 failed at call 1780dfb7 (err=-28) " 1. fdtdec_get_alias_seq will use "video" as base, however in alias node, we use ipux, so add new alias for U-Boot dts. 2. DM_VIDEO is enabled, however reserve_video is called before relocation, so to make DM_VIDEO work before relocation, need to set SYS_MALLOC_F_LEN 3. defconfig is updated with savedefconfig Note: I do not have a video panel to test, but with this patch, U-Boot boots up again, below log. " U-Boot SPL 2019.04-00662-g0b62453bff (Apr 25 2019 - 10:36:31 +0800) Trying to boot from MMC1 U-Boot 2019.04-00662-g0b62453bff (Apr 25 2019 - 10:36:31 +0800) CPU: Freescale i.MX6Q rev1.5 996 MHz (running at 792 MHz) CPU: Automotive temperature grade (-40C to 125C) at 34C Reset cause: POR Model: Freescale i.MX6 Quad SABRE Smart Device Board Board: MX6-SabreSD I2C: ready DRAM: 1 GiB PMIC: PFUZE100 ID=0x10 MMC: FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 3 Loading Environment from MMC... *** Warning - bad CRC, using default environment PCI: pcie phy link never came up In: serial Out: serial Err: serial Net: FEC [PRIME] Hit any key to stop autoboot: 0 " Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Anatolij Gustschin <agust@denx.de>
545 lines
11 KiB
Plaintext
545 lines
11 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0
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//
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// Copyright 2013 Freescale Semiconductor, Inc.
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#include <dt-bindings/interrupt-controller/irq.h>
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#include "imx6q-pinfunc.h"
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#include "imx6qdl.dtsi"
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/ {
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aliases {
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ipu1 = &ipu2;
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video1 = &ipu2;
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spi4 = &ecspi5;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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compatible = "arm,cortex-a9";
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device_type = "cpu";
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reg = <0>;
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next-level-cache = <&L2>;
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operating-points = <
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/* kHz uV */
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1200000 1275000
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996000 1250000
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852000 1250000
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792000 1175000
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396000 975000
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>;
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fsl,soc-operating-points = <
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/* ARM kHz SOC-PU uV */
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1200000 1275000
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996000 1250000
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852000 1250000
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792000 1175000
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396000 1175000
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>;
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clock-latency = <61036>; /* two CLK32 periods */
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#cooling-cells = <2>;
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clocks = <&clks IMX6QDL_CLK_ARM>,
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<&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
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<&clks IMX6QDL_CLK_STEP>,
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<&clks IMX6QDL_CLK_PLL1_SW>,
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<&clks IMX6QDL_CLK_PLL1_SYS>;
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clock-names = "arm", "pll2_pfd2_396m", "step",
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"pll1_sw", "pll1_sys";
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arm-supply = <®_arm>;
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pu-supply = <®_pu>;
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soc-supply = <®_soc>;
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};
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cpu1: cpu@1 {
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compatible = "arm,cortex-a9";
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device_type = "cpu";
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reg = <1>;
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next-level-cache = <&L2>;
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operating-points = <
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/* kHz uV */
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1200000 1275000
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996000 1250000
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852000 1250000
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792000 1175000
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396000 975000
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>;
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fsl,soc-operating-points = <
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/* ARM kHz SOC-PU uV */
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1200000 1275000
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996000 1250000
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852000 1250000
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792000 1175000
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396000 1175000
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>;
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clock-latency = <61036>; /* two CLK32 periods */
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clocks = <&clks IMX6QDL_CLK_ARM>,
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<&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
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<&clks IMX6QDL_CLK_STEP>,
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<&clks IMX6QDL_CLK_PLL1_SW>,
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<&clks IMX6QDL_CLK_PLL1_SYS>;
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clock-names = "arm", "pll2_pfd2_396m", "step",
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"pll1_sw", "pll1_sys";
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arm-supply = <®_arm>;
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pu-supply = <®_pu>;
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soc-supply = <®_soc>;
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};
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cpu2: cpu@2 {
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compatible = "arm,cortex-a9";
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device_type = "cpu";
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reg = <2>;
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next-level-cache = <&L2>;
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operating-points = <
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/* kHz uV */
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1200000 1275000
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996000 1250000
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852000 1250000
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792000 1175000
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396000 975000
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>;
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fsl,soc-operating-points = <
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/* ARM kHz SOC-PU uV */
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1200000 1275000
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996000 1250000
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852000 1250000
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792000 1175000
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396000 1175000
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>;
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clock-latency = <61036>; /* two CLK32 periods */
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clocks = <&clks IMX6QDL_CLK_ARM>,
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<&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
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<&clks IMX6QDL_CLK_STEP>,
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<&clks IMX6QDL_CLK_PLL1_SW>,
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<&clks IMX6QDL_CLK_PLL1_SYS>;
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clock-names = "arm", "pll2_pfd2_396m", "step",
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"pll1_sw", "pll1_sys";
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arm-supply = <®_arm>;
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pu-supply = <®_pu>;
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soc-supply = <®_soc>;
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};
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cpu3: cpu@3 {
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compatible = "arm,cortex-a9";
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device_type = "cpu";
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reg = <3>;
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next-level-cache = <&L2>;
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operating-points = <
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/* kHz uV */
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1200000 1275000
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996000 1250000
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852000 1250000
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792000 1175000
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396000 975000
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>;
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fsl,soc-operating-points = <
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/* ARM kHz SOC-PU uV */
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1200000 1275000
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996000 1250000
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852000 1250000
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792000 1175000
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396000 1175000
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>;
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clock-latency = <61036>; /* two CLK32 periods */
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clocks = <&clks IMX6QDL_CLK_ARM>,
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<&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
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<&clks IMX6QDL_CLK_STEP>,
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<&clks IMX6QDL_CLK_PLL1_SW>,
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<&clks IMX6QDL_CLK_PLL1_SYS>;
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clock-names = "arm", "pll2_pfd2_396m", "step",
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"pll1_sw", "pll1_sys";
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arm-supply = <®_arm>;
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pu-supply = <®_pu>;
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soc-supply = <®_soc>;
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};
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};
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soc {
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ocram: sram@900000 {
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compatible = "mmio-sram";
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reg = <0x00900000 0x40000>;
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clocks = <&clks IMX6QDL_CLK_OCRAM>;
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};
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aips-bus@2000000 { /* AIPS1 */
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spba-bus@2000000 {
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ecspi5: spi@2018000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
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reg = <0x02018000 0x4000>;
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interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks IMX6Q_CLK_ECSPI5>,
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<&clks IMX6Q_CLK_ECSPI5>;
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clock-names = "ipg", "per";
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dmas = <&sdma 11 8 1>, <&sdma 12 8 2>;
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dma-names = "rx", "tx";
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status = "disabled";
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};
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};
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iomuxc: iomuxc@20e0000 {
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compatible = "fsl,imx6q-iomuxc";
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};
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};
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sata: sata@2200000 {
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compatible = "fsl,imx6q-ahci";
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reg = <0x02200000 0x4000>;
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interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks IMX6QDL_CLK_SATA>,
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<&clks IMX6QDL_CLK_SATA_REF_100M>,
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<&clks IMX6QDL_CLK_AHB>;
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clock-names = "sata", "sata_ref", "ahb";
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status = "disabled";
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};
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gpu_vg: gpu@2204000 {
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compatible = "vivante,gc";
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reg = <0x02204000 0x4000>;
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interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks IMX6QDL_CLK_OPENVG_AXI>,
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<&clks IMX6QDL_CLK_GPU2D_CORE>;
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clock-names = "bus", "core";
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power-domains = <&pd_pu>;
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#cooling-cells = <2>;
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};
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ipu2: ipu@2800000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,imx6q-ipu";
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reg = <0x02800000 0x400000>;
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interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>,
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<0 7 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks IMX6QDL_CLK_IPU2>,
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<&clks IMX6QDL_CLK_IPU2_DI0>,
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<&clks IMX6QDL_CLK_IPU2_DI1>;
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clock-names = "bus", "di0", "di1";
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resets = <&src 4>;
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ipu2_csi0: port@0 {
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reg = <0>;
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ipu2_csi0_from_mipi_vc2: endpoint {
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remote-endpoint = <&mipi_vc2_to_ipu2_csi0>;
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};
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};
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ipu2_csi1: port@1 {
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reg = <1>;
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ipu2_csi1_from_ipu2_csi1_mux: endpoint {
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remote-endpoint = <&ipu2_csi1_mux_to_ipu2_csi1>;
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};
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};
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ipu2_di0: port@2 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <2>;
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ipu2_di0_disp0: endpoint@0 {
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reg = <0>;
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};
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ipu2_di0_hdmi: endpoint@1 {
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reg = <1>;
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remote-endpoint = <&hdmi_mux_2>;
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};
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ipu2_di0_mipi: endpoint@2 {
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reg = <2>;
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remote-endpoint = <&mipi_mux_2>;
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};
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ipu2_di0_lvds0: endpoint@3 {
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reg = <3>;
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remote-endpoint = <&lvds0_mux_2>;
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};
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ipu2_di0_lvds1: endpoint@4 {
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reg = <4>;
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remote-endpoint = <&lvds1_mux_2>;
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};
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};
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ipu2_di1: port@3 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <3>;
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ipu2_di1_hdmi: endpoint@1 {
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reg = <1>;
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remote-endpoint = <&hdmi_mux_3>;
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};
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ipu2_di1_mipi: endpoint@2 {
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reg = <2>;
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remote-endpoint = <&mipi_mux_3>;
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};
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ipu2_di1_lvds0: endpoint@3 {
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reg = <3>;
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remote-endpoint = <&lvds0_mux_3>;
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};
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ipu2_di1_lvds1: endpoint@4 {
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reg = <4>;
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remote-endpoint = <&lvds1_mux_3>;
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};
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};
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};
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};
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capture-subsystem {
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compatible = "fsl,imx-capture-subsystem";
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ports = <&ipu1_csi0>, <&ipu1_csi1>, <&ipu2_csi0>, <&ipu2_csi1>;
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};
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display-subsystem {
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compatible = "fsl,imx-display-subsystem";
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ports = <&ipu1_di0>, <&ipu1_di1>, <&ipu2_di0>, <&ipu2_di1>;
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};
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};
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&gpio1 {
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gpio-ranges = <&iomuxc 0 136 2>, <&iomuxc 2 141 1>, <&iomuxc 3 139 1>,
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<&iomuxc 4 142 2>, <&iomuxc 6 140 1>, <&iomuxc 7 144 2>,
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<&iomuxc 9 138 1>, <&iomuxc 10 213 3>, <&iomuxc 13 20 1>,
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<&iomuxc 14 19 1>, <&iomuxc 15 21 1>, <&iomuxc 16 208 1>,
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<&iomuxc 17 207 1>, <&iomuxc 18 210 3>, <&iomuxc 21 209 1>,
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<&iomuxc 22 116 10>;
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};
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&gpio2 {
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gpio-ranges = <&iomuxc 0 191 16>, <&iomuxc 16 55 14>, <&iomuxc 30 35 1>,
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<&iomuxc 31 44 1>;
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};
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&gpio3 {
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gpio-ranges = <&iomuxc 0 69 16>, <&iomuxc 16 36 8>, <&iomuxc 24 45 8>;
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};
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&gpio4 {
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gpio-ranges = <&iomuxc 5 149 1>, <&iomuxc 6 126 10>, <&iomuxc 16 87 16>;
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};
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&gpio5 {
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gpio-ranges = <&iomuxc 0 85 1>, <&iomuxc 2 34 1>, <&iomuxc 4 53 1>,
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<&iomuxc 5 103 13>, <&iomuxc 18 150 14>;
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};
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&gpio6 {
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gpio-ranges = <&iomuxc 0 164 6>, <&iomuxc 6 54 1>, <&iomuxc 7 181 5>,
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<&iomuxc 14 186 3>, <&iomuxc 17 170 2>, <&iomuxc 19 22 12>,
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<&iomuxc 31 86 1>;
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};
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&gpio7 {
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gpio-ranges = <&iomuxc 0 172 9>, <&iomuxc 9 189 2>, <&iomuxc 11 146 3>;
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};
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&gpr {
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ipu1_csi0_mux {
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compatible = "video-mux";
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mux-controls = <&mux 0>;
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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ipu1_csi0_mux_from_mipi_vc0: endpoint {
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remote-endpoint = <&mipi_vc0_to_ipu1_csi0_mux>;
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};
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};
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port@1 {
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reg = <1>;
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ipu1_csi0_mux_from_parallel_sensor: endpoint {
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};
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};
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port@2 {
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reg = <2>;
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ipu1_csi0_mux_to_ipu1_csi0: endpoint {
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remote-endpoint = <&ipu1_csi0_from_ipu1_csi0_mux>;
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};
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};
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};
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ipu2_csi1_mux {
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compatible = "video-mux";
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mux-controls = <&mux 1>;
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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ipu2_csi1_mux_from_mipi_vc3: endpoint {
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remote-endpoint = <&mipi_vc3_to_ipu2_csi1_mux>;
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};
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};
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port@1 {
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reg = <1>;
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ipu2_csi1_mux_from_parallel_sensor: endpoint {
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};
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};
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port@2 {
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reg = <2>;
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ipu2_csi1_mux_to_ipu2_csi1: endpoint {
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remote-endpoint = <&ipu2_csi1_from_ipu2_csi1_mux>;
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};
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};
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};
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};
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&hdmi {
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compatible = "fsl,imx6q-hdmi";
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port@2 {
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reg = <2>;
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hdmi_mux_2: endpoint {
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remote-endpoint = <&ipu2_di0_hdmi>;
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};
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};
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port@3 {
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reg = <3>;
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hdmi_mux_3: endpoint {
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remote-endpoint = <&ipu2_di1_hdmi>;
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};
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};
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};
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&ipu1_csi1 {
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ipu1_csi1_from_mipi_vc1: endpoint {
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remote-endpoint = <&mipi_vc1_to_ipu1_csi1>;
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};
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};
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&ldb {
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clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
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<&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>,
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<&clks IMX6QDL_CLK_IPU2_DI0_SEL>, <&clks IMX6QDL_CLK_IPU2_DI1_SEL>,
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<&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>;
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clock-names = "di0_pll", "di1_pll",
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"di0_sel", "di1_sel", "di2_sel", "di3_sel",
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"di0", "di1";
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lvds-channel@0 {
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port@2 {
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reg = <2>;
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lvds0_mux_2: endpoint {
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remote-endpoint = <&ipu2_di0_lvds0>;
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};
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};
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port@3 {
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reg = <3>;
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lvds0_mux_3: endpoint {
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remote-endpoint = <&ipu2_di1_lvds0>;
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};
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};
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};
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lvds-channel@1 {
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port@2 {
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reg = <2>;
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lvds1_mux_2: endpoint {
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remote-endpoint = <&ipu2_di0_lvds1>;
|
|
};
|
|
};
|
|
|
|
port@3 {
|
|
reg = <3>;
|
|
|
|
lvds1_mux_3: endpoint {
|
|
remote-endpoint = <&ipu2_di1_lvds1>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
&mipi_csi {
|
|
port@1 {
|
|
reg = <1>;
|
|
|
|
mipi_vc0_to_ipu1_csi0_mux: endpoint {
|
|
remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc0>;
|
|
};
|
|
};
|
|
|
|
port@2 {
|
|
reg = <2>;
|
|
|
|
mipi_vc1_to_ipu1_csi1: endpoint {
|
|
remote-endpoint = <&ipu1_csi1_from_mipi_vc1>;
|
|
};
|
|
};
|
|
|
|
port@3 {
|
|
reg = <3>;
|
|
|
|
mipi_vc2_to_ipu2_csi0: endpoint {
|
|
remote-endpoint = <&ipu2_csi0_from_mipi_vc2>;
|
|
};
|
|
};
|
|
|
|
port@4 {
|
|
reg = <4>;
|
|
|
|
mipi_vc3_to_ipu2_csi1_mux: endpoint {
|
|
remote-endpoint = <&ipu2_csi1_mux_from_mipi_vc3>;
|
|
};
|
|
};
|
|
};
|
|
|
|
&mipi_dsi {
|
|
ports {
|
|
port@2 {
|
|
reg = <2>;
|
|
|
|
mipi_mux_2: endpoint {
|
|
remote-endpoint = <&ipu2_di0_mipi>;
|
|
};
|
|
};
|
|
|
|
port@3 {
|
|
reg = <3>;
|
|
|
|
mipi_mux_3: endpoint {
|
|
remote-endpoint = <&ipu2_di1_mipi>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
&mux {
|
|
mux-reg-masks = <0x04 0x00080000>, /* MIPI_IPU1_MUX */
|
|
<0x04 0x00100000>, /* MIPI_IPU2_MUX */
|
|
<0x0c 0x0000000c>, /* HDMI_MUX_CTL */
|
|
<0x0c 0x000000c0>, /* LVDS0_MUX_CTL */
|
|
<0x0c 0x00000300>, /* LVDS1_MUX_CTL */
|
|
<0x28 0x00000003>, /* DCIC1_MUX_CTL */
|
|
<0x28 0x0000000c>; /* DCIC2_MUX_CTL */
|
|
};
|
|
|
|
&vpu {
|
|
compatible = "fsl,imx6q-vpu", "cnm,coda960";
|
|
};
|