mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-31 06:18:51 +09:00
![Luca Ceresoli](/assets/img/avatar_default.png)
Avnet UltraZed-EV Starter Kit is composed by the UltraZed-EV SoM and the
only publicly-available compatible carrier card. The SoM is based on the EV
version of the Xilinx ZynqMP SoC+FPGA.
The psu_init_gpl.c file has been generated from the board definition files
at [0] using Vivado 2018.3 and then minimized by
tools/zynqmp_psu_init_minimize.sh. Manually removed serdes init code since
it is not mentioned in device tree and fixed a checkpatch error.
[0] 3686c9ff7d/ultrazed_7ev_cc/1.1
Signed-off-by: Luca Ceresoli <luca@lucaceresoli.net>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
57 lines
1.0 KiB
Plaintext
57 lines
1.0 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0+ OR X11
|
|
|
|
/*
|
|
* UltraZed-EV SoM v1
|
|
* http://ultrazed.org/product/ultrazed-ev
|
|
*/
|
|
|
|
/dts-v1/;
|
|
|
|
#include "zynqmp.dtsi"
|
|
#include "zynqmp-clk-ccf.dtsi"
|
|
|
|
/ {
|
|
model = "Avnet UltraZed EV SoM v1.0";
|
|
compatible = "avnet,ultrazedev-som-v1.0", "xlnx,zynqmp";
|
|
memory {
|
|
device_type = "memory";
|
|
reg = <0x0 0x0 0x0 0x80000000>, /* 2 GB @ offset 0 */
|
|
<0x8 0x0 0x0 0x80000000>; /* 2 GB @ offset 32GB */
|
|
};
|
|
};
|
|
|
|
&i2c1 {
|
|
clock-frequency = <400000>;
|
|
status = "okay";
|
|
|
|
i2cswitch@70 {
|
|
compatible = "nxp,pca9543";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <0x70>;
|
|
|
|
/* I2C connected to Carrier Card via JX3A1/JX3C1 */
|
|
i2c_cc: i2c@0 {
|
|
reg = <0>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
};
|
|
};
|
|
|
|
/* Marvell 88E1512-A0-NNP2I000 Ethernet PHY */
|
|
&gem3 {
|
|
phy-mode = "rgmii-id";
|
|
phy-handle = <&gem3phy>;
|
|
gem3phy: ethernet-phy@0 {
|
|
reg = <0>;
|
|
};
|
|
};
|
|
|
|
/* Micron MTFC8GAKAJCN-4M 8 GB eMMC */
|
|
&sdhci0 {
|
|
status = "okay";
|
|
xlnx,mio_bank = <0>;
|
|
clock-frequency = <199998000>;
|
|
};
|