mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-14 15:16:16 +09:00
a66e4d00df
Because the MACB driver supports the driver model and device tree, the pins configuration and clock enabling are handled by the pinctrl driver and clock driver, remove this hardcoded init code. The USB Ether init code is removed as well. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
307 lines
7.4 KiB
C
307 lines
7.4 KiB
C
/*
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* Copyright (C) 2015 Atmel Corporation
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* Wenyou.Yang <wenyou.yang@atmel.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <atmel_hlcdc.h>
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#include <debug_uart.h>
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#include <dm.h>
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#include <i2c.h>
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#include <lcd.h>
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#include <mmc.h>
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#include <spi.h>
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#include <version.h>
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#include <asm/io.h>
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#include <asm/arch/at91_common.h>
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#include <asm/arch/atmel_pio4.h>
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#include <asm/arch/atmel_mpddrc.h>
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#include <asm/arch/atmel_sdhci.h>
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#include <asm/arch/clk.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/sama5d2.h>
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DECLARE_GLOBAL_DATA_PTR;
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static void board_usb_hw_init(void)
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{
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atmel_pio4_set_pio_output(AT91_PIO_PORTB, 10, 1);
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}
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#ifdef CONFIG_LCD
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vidinfo_t panel_info = {
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.vl_col = 480,
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.vl_row = 272,
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.vl_clk = 9000000,
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.vl_bpix = LCD_BPP,
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.vl_tft = 1,
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.vl_hsync_len = 41,
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.vl_left_margin = 2,
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.vl_right_margin = 2,
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.vl_vsync_len = 11,
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.vl_upper_margin = 2,
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.vl_lower_margin = 2,
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.mmio = ATMEL_BASE_LCDC,
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};
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/* No power up/down pin for the LCD pannel */
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void lcd_enable(void) { /* Empty! */ }
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void lcd_disable(void) { /* Empty! */ }
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unsigned int has_lcdc(void)
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{
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return 1;
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}
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static void board_lcd_hw_init(void)
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{
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atmel_pio4_set_a_periph(AT91_PIO_PORTC, 28, 0); /* LCDPWM */
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atmel_pio4_set_a_periph(AT91_PIO_PORTC, 29, 0); /* LCDDISP */
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atmel_pio4_set_a_periph(AT91_PIO_PORTC, 30, 0); /* LCDVSYNC */
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atmel_pio4_set_a_periph(AT91_PIO_PORTC, 31, 0); /* LCDHSYNC */
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atmel_pio4_set_a_periph(AT91_PIO_PORTD, 0, 0); /* LCDPCK */
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atmel_pio4_set_a_periph(AT91_PIO_PORTD, 1, 0); /* LCDDEN */
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/* LCDDAT0 */
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/* LCDDAT1 */
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atmel_pio4_set_a_periph(AT91_PIO_PORTC, 10, 0); /* LCDDAT2 */
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atmel_pio4_set_a_periph(AT91_PIO_PORTC, 11, 0); /* LCDDAT3 */
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atmel_pio4_set_a_periph(AT91_PIO_PORTC, 12, 0); /* LCDDAT4 */
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atmel_pio4_set_a_periph(AT91_PIO_PORTC, 13, 0); /* LCDDAT5 */
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atmel_pio4_set_a_periph(AT91_PIO_PORTC, 14, 0); /* LCDDAT6 */
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atmel_pio4_set_a_periph(AT91_PIO_PORTC, 15, 0); /* LCDDAT7 */
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/* LCDDAT8 */
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/* LCDDAT9 */
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atmel_pio4_set_a_periph(AT91_PIO_PORTC, 16, 0); /* LCDDAT10 */
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atmel_pio4_set_a_periph(AT91_PIO_PORTC, 17, 0); /* LCDDAT11 */
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atmel_pio4_set_a_periph(AT91_PIO_PORTC, 18, 0); /* LCDDAT12 */
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atmel_pio4_set_a_periph(AT91_PIO_PORTC, 19, 0); /* LCDDAT13 */
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atmel_pio4_set_a_periph(AT91_PIO_PORTC, 20, 0); /* LCDDAT14 */
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atmel_pio4_set_a_periph(AT91_PIO_PORTC, 21, 0); /* LCDDAT15 */
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/* LCDD16 */
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/* LCDD17 */
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atmel_pio4_set_a_periph(AT91_PIO_PORTC, 22, 0); /* LCDDAT18 */
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atmel_pio4_set_a_periph(AT91_PIO_PORTC, 23, 0); /* LCDDAT19 */
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atmel_pio4_set_a_periph(AT91_PIO_PORTC, 24, 0); /* LCDDAT20 */
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atmel_pio4_set_a_periph(AT91_PIO_PORTC, 25, 0); /* LCDDAT21 */
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atmel_pio4_set_a_periph(AT91_PIO_PORTC, 26, 0); /* LCDDAT22 */
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atmel_pio4_set_a_periph(AT91_PIO_PORTC, 27, 0); /* LCDDAT23 */
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at91_periph_clk_enable(ATMEL_ID_LCDC);
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}
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#ifdef CONFIG_LCD_INFO
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void lcd_show_board_info(void)
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{
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ulong dram_size;
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int i;
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char temp[32];
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lcd_printf("%s\n", U_BOOT_VERSION);
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lcd_printf("2015 ATMEL Corp\n");
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lcd_printf("%s CPU at %s MHz\n", get_cpu_name(),
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strmhz(temp, get_cpu_clk_rate()));
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dram_size = 0;
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for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
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dram_size += gd->bd->bi_dram[i].size;
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lcd_printf("%ld MB SDRAM\n", dram_size >> 20);
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}
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#endif /* CONFIG_LCD_INFO */
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#endif /* CONFIG_LCD */
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static void board_uart1_hw_init(void)
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{
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atmel_pio4_set_a_periph(AT91_PIO_PORTD, 2, 1); /* URXD1 */
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atmel_pio4_set_a_periph(AT91_PIO_PORTD, 3, 0); /* UTXD1 */
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at91_periph_clk_enable(ATMEL_ID_UART1);
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}
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#ifdef CONFIG_DEBUG_UART_BOARD_INIT
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void board_debug_uart_init(void)
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{
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board_uart1_hw_init();
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}
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#endif
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#ifdef CONFIG_BOARD_EARLY_INIT_F
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int board_early_init_f(void)
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{
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#ifdef CONFIG_DEBUG_UART
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debug_uart_init();
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#else
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board_uart1_hw_init();
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#endif
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return 0;
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}
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#endif
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int board_init(void)
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{
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/* address of boot parameters */
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gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
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#ifdef CONFIG_LCD
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board_lcd_hw_init();
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#endif
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#ifdef CONFIG_CMD_USB
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board_usb_hw_init();
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#endif
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return 0;
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}
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int dram_init(void)
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{
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gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
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CONFIG_SYS_SDRAM_SIZE);
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return 0;
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}
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#ifdef CONFIG_CMD_I2C
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static int set_ethaddr_from_eeprom(void)
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{
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const int ETH_ADDR_LEN = 6;
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unsigned char ethaddr[ETH_ADDR_LEN];
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const char *ETHADDR_NAME = "ethaddr";
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struct udevice *bus, *dev;
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if (getenv(ETHADDR_NAME))
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return 0;
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if (uclass_get_device_by_seq(UCLASS_I2C, 1, &bus)) {
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printf("Cannot find I2C bus 1\n");
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return -1;
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}
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if (dm_i2c_probe(bus, AT24MAC_ADDR, 0, &dev)) {
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printf("Failed to probe I2C chip\n");
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return -1;
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}
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if (dm_i2c_read(dev, AT24MAC_REG, ethaddr, ETH_ADDR_LEN)) {
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printf("Failed to read ethernet address from EEPROM\n");
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return -1;
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}
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if (!is_valid_ethaddr(ethaddr)) {
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printf("The ethernet address read from EEPROM is not valid!\n");
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return -1;
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}
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return eth_setenv_enetaddr(ETHADDR_NAME, ethaddr);
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}
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#else
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static int set_ethaddr_from_eeprom(void)
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{
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return 0;
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}
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#endif
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#ifdef CONFIG_MISC_INIT_R
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int misc_init_r(void)
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{
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set_ethaddr_from_eeprom();
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return 0;
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}
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#endif
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/* SPL */
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#ifdef CONFIG_SPL_BUILD
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void spl_board_init(void)
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{
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}
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static void ddrc_conf(struct atmel_mpddrc_config *ddrc)
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{
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ddrc->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR3_SDRAM);
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ddrc->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
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ATMEL_MPDDRC_CR_NR_ROW_14 |
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ATMEL_MPDDRC_CR_CAS_DDR_CAS5 |
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ATMEL_MPDDRC_CR_DIC_DS |
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ATMEL_MPDDRC_CR_DIS_DLL |
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ATMEL_MPDDRC_CR_NB_8BANKS |
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ATMEL_MPDDRC_CR_DECOD_INTERLEAVED |
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ATMEL_MPDDRC_CR_UNAL_SUPPORTED);
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ddrc->rtr = 0x511;
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ddrc->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |
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3 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |
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4 << ATMEL_MPDDRC_TPR0_TWR_OFFSET |
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9 << ATMEL_MPDDRC_TPR0_TRC_OFFSET |
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3 << ATMEL_MPDDRC_TPR0_TRP_OFFSET |
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4 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET |
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4 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET |
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4 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET);
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ddrc->tpr1 = (27 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET |
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29 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
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0 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
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3 << ATMEL_MPDDRC_TPR1_TXP_OFFSET);
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ddrc->tpr2 = (0 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET |
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0 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
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0 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
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4 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
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7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET);
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}
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void mem_init(void)
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{
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struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
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struct atmel_mpddr *mpddrc = (struct atmel_mpddr *)ATMEL_BASE_MPDDRC;
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struct atmel_mpddrc_config ddrc_config;
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u32 reg;
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ddrc_conf(&ddrc_config);
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at91_periph_clk_enable(ATMEL_ID_MPDDRC);
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writel(AT91_PMC_DDR, &pmc->scer);
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reg = readl(&mpddrc->io_calibr);
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reg &= ~ATMEL_MPDDRC_IO_CALIBR_RDIV;
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reg |= ATMEL_MPDDRC_IO_CALIBR_DDR3_RZQ_55;
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reg &= ~ATMEL_MPDDRC_IO_CALIBR_TZQIO;
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reg |= ATMEL_MPDDRC_IO_CALIBR_TZQIO_(100);
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writel(reg, &mpddrc->io_calibr);
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writel(ATMEL_MPDDRC_RD_DATA_PATH_SHIFT_TWO_CYCLE,
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&mpddrc->rd_data_path);
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ddr3_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddrc_config);
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writel(0x3, &mpddrc->cal_mr4);
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writel(64, &mpddrc->tim_cal);
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}
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void at91_pmc_init(void)
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{
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struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
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u32 tmp;
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tmp = AT91_PMC_PLLAR_29 |
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AT91_PMC_PLLXR_PLLCOUNT(0x3f) |
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AT91_PMC_PLLXR_MUL(82) |
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AT91_PMC_PLLXR_DIV(1);
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at91_plla_init(tmp);
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writel(0x0 << 8, &pmc->pllicpr);
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tmp = AT91_PMC_MCKR_H32MXDIV |
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AT91_PMC_MCKR_PLLADIV_2 |
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AT91_PMC_MCKR_MDIV_3 |
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AT91_PMC_MCKR_CSS_PLLA;
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at91_mck_init(tmp);
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}
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#endif
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