mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-23 11:29:43 +09:00
a633a18f90
A chache API of SH is developped by reference in linux kernel. And API was the same as the linux kernel. This patch change cache API to defines as U-Boot. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
32 lines
671 B
C
32 lines
671 B
C
#ifndef __ASM_SH_CACHE_H
|
|
#define __ASM_SH_CACHE_H
|
|
|
|
#if defined(CONFIG_SH4) || defined(CONFIG_SH4A)
|
|
|
|
int cache_control(unsigned int cmd);
|
|
|
|
#define L1_CACHE_BYTES 32
|
|
|
|
struct __large_struct { unsigned long buf[100]; };
|
|
#define __m(x) (*(struct __large_struct *)(x))
|
|
|
|
#else
|
|
|
|
/*
|
|
* 32-bytes is the largest L1 data cache line size for SH the architecture. So
|
|
* it is a safe default for DMA alignment.
|
|
*/
|
|
#define ARCH_DMA_MINALIGN 32
|
|
|
|
#endif /* CONFIG_SH4 || CONFIG_SH4A */
|
|
|
|
/*
|
|
* Use the L1 data cache line size value for the minimum DMA buffer alignment
|
|
* on SH.
|
|
*/
|
|
#ifndef ARCH_DMA_MINALIGN
|
|
#define ARCH_DMA_MINALIGN L1_CACHE_BYTES
|
|
#endif
|
|
|
|
#endif /* __ASM_SH_CACHE_H */
|