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https://github.com/brain-hackers/u-boot-brain
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e76cd5d4cf
There were a number of shared files that were using CONFIG_SYS_MPC85xx_DDR_ADDR, or CONFIG_SYS_MPC86xx_DDR_ADDR, and several variants (DDR2, DDR3). A recent patchset added 85xx-specific ones to code which was used by 86xx systems. After reviewing places where these constants were used, and noting that the type definitions of the pointers assigned to point to those addresses were the same, the cleanest approach to fixing this problem was to unify the namespace for the 85xx, 83xx, and 86xx DDR address definitions. This patch does: s/CONFIG_SYS_MPC8.xx_DDR/CONFIG_SYS_MPC8xxx_DDR/g All 85xx, 86xx, and 83xx have been built with this change. Signed-off-by: Andy Fleming <afleming@freescale.com> Tested-by: Andy Fleming <afleming@freescale.com> Acked-by: Kim Phillips <kim.phillips@freescale.com>
137 lines
4.0 KiB
C
137 lines
4.0 KiB
C
/*
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* Copyright 2011 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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*
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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*/
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#include <common.h>
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#include <ns16550.h>
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#include <asm/io.h>
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#include <nand.h>
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#include <linux/compiler.h>
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#include <asm/fsl_law.h>
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#include <asm/fsl_ddr_sdram.h>
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#include <asm/global_data.h>
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DECLARE_GLOBAL_DATA_PTR;
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#ifndef CONFIG_SYS_INIT_L2_ADDR
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/*
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* Fixed sdram init -- doesn't use serial presence detect.
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*/
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static void sdram_init(void)
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{
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ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
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__raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds);
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__raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config);
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#if CONFIG_CHIP_SELECTS_PER_CTRL > 1
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__raw_writel(CONFIG_SYS_DDR_CS1_BNDS, &ddr->cs1_bnds);
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__raw_writel(CONFIG_SYS_DDR_CS1_CONFIG, &ddr->cs1_config);
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#endif
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__raw_writel(CONFIG_SYS_DDR_TIMING_3, &ddr->timing_cfg_3);
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__raw_writel(CONFIG_SYS_DDR_TIMING_0, &ddr->timing_cfg_0);
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__raw_writel(CONFIG_SYS_DDR_TIMING_1, &ddr->timing_cfg_1);
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__raw_writel(CONFIG_SYS_DDR_TIMING_2, &ddr->timing_cfg_2);
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__raw_writel(CONFIG_SYS_DDR_CONTROL_2, &ddr->sdram_cfg_2);
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__raw_writel(CONFIG_SYS_DDR_MODE_1, &ddr->sdram_mode);
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__raw_writel(CONFIG_SYS_DDR_MODE_2, &ddr->sdram_mode_2);
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__raw_writel(CONFIG_SYS_DDR_INTERVAL, &ddr->sdram_interval);
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__raw_writel(CONFIG_SYS_DDR_DATA_INIT, &ddr->sdram_data_init);
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__raw_writel(CONFIG_SYS_DDR_CLK_CTRL, &ddr->sdram_clk_cntl);
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__raw_writel(CONFIG_SYS_DDR_TIMING_4, &ddr->timing_cfg_4);
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__raw_writel(CONFIG_SYS_DDR_TIMING_5, &ddr->timing_cfg_5);
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__raw_writel(CONFIG_SYS_DDR_ZQ_CONTROL, &ddr->ddr_zq_cntl);
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__raw_writel(CONFIG_SYS_DDR_WRLVL_CONTROL, &ddr->ddr_wrlvl_cntl);
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/* Set, but do not enable the memory */
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__raw_writel(CONFIG_SYS_DDR_CONTROL & ~SDRAM_CFG_MEM_EN, &ddr->sdram_cfg);
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asm volatile("sync;isync");
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udelay(500);
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/* Let the controller go */
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out_be32(&ddr->sdram_cfg, in_be32(&ddr->sdram_cfg) | SDRAM_CFG_MEM_EN);
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set_next_law(0, CONFIG_SYS_SDRAM_SIZE_LAW, LAW_TRGT_IF_DDR_1);
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}
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#endif
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void board_init_f(ulong bootflag)
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{
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u32 plat_ratio;
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ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
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#ifndef CONFIG_QE
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ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
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#endif
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/* initialize selected port with appropriate baud rate */
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plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
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plat_ratio >>= 1;
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gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
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NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
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gd->bus_clk / 16 / CONFIG_BAUDRATE);
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puts("\nNAND boot... ");
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#ifndef CONFIG_QE
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/* init DDR3 reset signal */
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__raw_writel(0x02000000, &pgpio->gpdir);
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__raw_writel(0x00200000, &pgpio->gpodr);
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__raw_writel(0x00000000, &pgpio->gpdat);
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udelay(1000);
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__raw_writel(0x00200000, &pgpio->gpdat);
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udelay(1000);
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__raw_writel(0x00000000, &pgpio->gpdir);
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#endif
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#ifndef CONFIG_SYS_INIT_L2_ADDR
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/* Initialize the DDR3 */
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sdram_init();
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#endif
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/* copy code to RAM and jump to it - this should not return */
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/* NOTE - code has to be copied out of NAND buffer before
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* other blocks can be read.
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*/
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relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
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}
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void board_init_r(gd_t *gd, ulong dest_addr)
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{
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nand_boot();
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}
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void putc(char c)
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{
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if (c == '\n')
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NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r');
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NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c);
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}
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void puts(const char *str)
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{
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while (*str)
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putc(*str++);
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}
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