u-boot-brain/arch/arm
Nishanth Menon a615d0be6a ARM: Introduce erratum workaround for 801819
Add workaround for Cortex-A15 ARM erratum 801819 which says in summary
that "A livelock can occur in the L2 cache arbitration that might
prevent a snoop from completing. Under certain conditions this can
cause the system to deadlock. "

Recommended workaround is as follows:
Do both of the following:

1) Do not use the write-back no-allocate memory type.
2) Do not issue write-back cacheable stores at any time when the cache
is disabled (SCTLR.C=0) and the MMU is enabled (SCTLR.M=1). Because it
is implementation defined whether cacheable stores update the cache when
the cache is disabled it is not expected that any portable code will
execute cacheable stores when the cache is disabled.

For implementations of Cortex-A15 configured without the “L2 arbitration
register slice” option (typically one or two core systems), you must
also do the following:

3) Disable write-streaming in each CPU by setting ACTLR[28:25] = 0b1111

So, we provide an option to disable write streaming on OMAP5 and DRA7.
It is a rare condition to occur and may be enabled selectively based
on platform acceptance of risk.

Applies to: A15 revisions r2p0, r2p1, r2p2, r2p3 or r2p4 and REVIDR[3]
is set to 0.

Note: certain unicore SoCs *might* not have REVIDR[3] not set, but
might not meet the condition for the erratum to occur when they donot
have ACP (Accelerator Coherency Port) hooked to ACE (AXI Coherency
Extensions). Such SoCs will need the work around handled in the SoC
specific manner, since there is no ARM generic manner to detect such
configurations.

Based on ARM errata Document revision 18.0 (22 Nov 2013)

Suggested-by: Richard Woodruff <r-woodruff2@ti.com>
Suggested-by: Brad Griffis <bgriffis@ti.com>
Reviewed-by: Brad Griffis <bgriffis@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
2015-08-12 20:47:49 -04:00
..
cpu ARM: Introduce erratum workaround for 801819 2015-08-12 20:47:49 -04:00
dts arm: dts: socfpga: Add mmc alias 2015-08-08 14:14:04 +02:00
imx-common imx-common: timer: add i.MX6UL support 2015-08-02 11:05:07 +02:00
include Correct License and Copyright information on few files 2015-08-12 20:47:46 -04:00
lib ARM: cache: implement a default weak flush_cache() function 2015-08-12 20:47:48 -04:00
mach-at91 arm, at91: support for sam9260 based smartweb board 2015-08-12 20:47:28 -04:00
mach-bcm283x arm/mach-bcm283x/mbox: Flush and invalidate dcache when using fw mailbox 2015-08-12 20:47:42 -04:00
mach-davinci arch: Make board selection choices optional 2015-05-12 18:10:02 -04:00
mach-highbank ARM: highbank: move SoC sources to mach-highbank 2015-02-21 08:23:51 -05:00
mach-integrator integrator: switch to DM serial port 2015-08-12 20:47:49 -04:00
mach-keystone keystone2: add wfi in to the core_spin loop 2015-07-27 15:01:57 -04:00
mach-kirkwood arch: Make board selection choices optional 2015-05-12 18:10:02 -04:00
mach-mvebu arm: mvebu: Add SPL SDIO/MMC boot support 2015-07-24 09:45:30 +02:00
mach-nomadik arch: Make board selection choices optional 2015-05-12 18:10:02 -04:00
mach-orion5x arch: Make board selection choices optional 2015-05-12 18:10:02 -04:00
mach-socfpga arm: socfpga: misc: Add support for printing FPGA type 2015-08-08 14:14:30 +02:00
mach-tegra ARM: tegra: Add p2371-0000 board 2015-08-06 10:50:04 -07:00
mach-uniphier ARM: UniPhier: add PH1-sLD3 SoC support 2015-07-23 23:42:22 +09:00
mach-versatile ARM: versatile: move SoC sources to mach-versatile 2015-02-21 08:23:51 -05:00
mach-zynq zynq: Rename struct clk_ops to zynq_clk_ops 2015-07-21 17:39:29 -06:00
mvebu-common arm: mvebu: Move mvebu-common into mach-mvebu 2015-05-05 14:28:29 +02:00
config.mk arm: Include the .got section in the binary 2015-05-14 18:49:34 -06:00
Kconfig integrator: switch to DM serial port 2015-08-12 20:47:49 -04:00
Kconfig.debug arm: debug: add Kconfig entries for lowlevel debug 2014-10-26 22:23:12 +01:00
Makefile spl, common, serial: build SPL without serial support 2015-08-12 20:47:13 -04:00