mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-22 10:59:43 +09:00
d2eaec6006
This value is not used by the network stack and is available in the global data, so stop passing it around. For the one legacy function that still expects it (init op on old Ethernet drivers) pass in the global pointer version directly to avoid changing that interface. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Reported-by: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org> (Trival fix to remove an unneeded variable declaration in 4xx_enet.c)
312 lines
7.8 KiB
C
312 lines
7.8 KiB
C
/*
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* (C) Copyright 2007-2008
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* Stelian Pop <stelian@popies.net>
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* Lead Tech Design <www.leadtechdesign.com>
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* Copyright (C) 2008 Ronetix Ilko Iliev (www.ronetix.at)
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* Copyright (C) 2009 Jean-Christopher PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <linux/sizes.h>
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#include <asm/io.h>
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#include <asm/gpio.h>
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#include <asm/arch/at91sam9_smc.h>
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#include <asm/arch/at91_common.h>
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#include <asm/arch/at91_pmc.h>
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#include <asm/arch/at91_rstc.h>
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#include <asm/arch/at91_matrix.h>
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#include <asm/arch/clk.h>
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#include <asm/arch/gpio.h>
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#include <lcd.h>
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#include <atmel_lcdc.h>
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#include <dataflash.h>
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#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_DRIVER_DM9000)
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#include <net.h>
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#endif
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#include <netdev.h>
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DECLARE_GLOBAL_DATA_PTR;
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/* ------------------------------------------------------------------------- */
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/*
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* Miscelaneous platform dependent initialisations
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*/
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#ifdef CONFIG_CMD_NAND
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static void pm9261_nand_hw_init(void)
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{
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unsigned long csa;
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struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
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struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
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struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
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/* Enable CS3 */
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csa = readl(&matrix->csa) | AT91_MATRIX_CSA_EBI_CS3A;
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writel(csa, &matrix->csa);
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/* Configure SMC CS3 for NAND/SmartMedia */
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writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
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AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
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&smc->cs[3].setup);
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writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
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AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
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&smc->cs[3].pulse);
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writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
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&smc->cs[3].cycle);
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writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
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AT91_SMC_MODE_EXNW_DISABLE |
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#ifdef CONFIG_SYS_NAND_DBW_16
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AT91_SMC_MODE_DBW_16 |
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#else /* CONFIG_SYS_NAND_DBW_8 */
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AT91_SMC_MODE_DBW_8 |
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#endif
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AT91_SMC_MODE_TDF_CYCLE(2),
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&smc->cs[3].mode);
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writel(1 << ATMEL_ID_PIOA |
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1 << ATMEL_ID_PIOC,
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&pmc->pcer);
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/* Configure RDY/BSY */
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gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
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/* Enable NandFlash */
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gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
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at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* NANDOE */
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at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* NANDWE */
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}
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#endif
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#ifdef CONFIG_DRIVER_DM9000
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static void pm9261_dm9000_hw_init(void)
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{
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struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
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struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
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/* Configure SMC CS2 for DM9000 */
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writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) |
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AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0),
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&smc->cs[2].setup);
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writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(8) |
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AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(8),
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&smc->cs[2].pulse);
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writel(AT91_SMC_CYCLE_NWE(16) | AT91_SMC_CYCLE_NRD(16),
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&smc->cs[2].cycle);
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writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
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AT91_SMC_MODE_EXNW_DISABLE |
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AT91_SMC_MODE_BAT | AT91_SMC_MODE_DBW_16 |
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AT91_SMC_MODE_TDF_CYCLE(1),
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&smc->cs[2].mode);
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/* Configure Interrupt pin as input, no pull-up */
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writel(1 << ATMEL_ID_PIOA, &pmc->pcer);
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at91_set_pio_input(AT91_PIO_PORTA, 24, 0);
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}
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#endif
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#ifdef CONFIG_LCD
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vidinfo_t panel_info = {
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.vl_col = 240,
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.vl_row = 320,
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.vl_clk = 4965000,
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.vl_sync = ATMEL_LCDC_INVLINE_INVERTED |
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ATMEL_LCDC_INVFRAME_INVERTED,
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.vl_bpix = 3,
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.vl_tft = 1,
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.vl_hsync_len = 5,
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.vl_left_margin = 1,
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.vl_right_margin = 33,
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.vl_vsync_len = 1,
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.vl_upper_margin = 1,
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.vl_lower_margin = 0,
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.mmio = ATMEL_BASE_LCDC,
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};
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void lcd_enable(void)
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{
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at91_set_pio_value(AT91_PIO_PORTA, 22, 0); /* power up */
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}
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void lcd_disable(void)
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{
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at91_set_pio_value(AT91_PIO_PORTA, 22, 1); /* power down */
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}
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static void pm9261_lcd_hw_init(void)
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{
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struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
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at91_set_a_periph(AT91_PIO_PORTB, 1, 0); /* LCDHSYNC */
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at91_set_a_periph(AT91_PIO_PORTB, 2, 0); /* LCDDOTCK */
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at91_set_a_periph(AT91_PIO_PORTB, 3, 0); /* LCDDEN */
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at91_set_a_periph(AT91_PIO_PORTB, 4, 0); /* LCDCC */
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at91_set_a_periph(AT91_PIO_PORTB, 7, 0); /* LCDD2 */
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at91_set_a_periph(AT91_PIO_PORTB, 8, 0); /* LCDD3 */
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at91_set_a_periph(AT91_PIO_PORTB, 9, 0); /* LCDD4 */
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at91_set_a_periph(AT91_PIO_PORTB, 10, 0); /* LCDD5 */
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at91_set_a_periph(AT91_PIO_PORTB, 11, 0); /* LCDD6 */
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at91_set_a_periph(AT91_PIO_PORTB, 12, 0); /* LCDD7 */
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at91_set_a_periph(AT91_PIO_PORTB, 15, 0); /* LCDD10 */
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at91_set_a_periph(AT91_PIO_PORTB, 16, 0); /* LCDD11 */
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at91_set_a_periph(AT91_PIO_PORTB, 17, 0); /* LCDD12 */
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at91_set_a_periph(AT91_PIO_PORTB, 18, 0); /* LCDD13 */
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at91_set_a_periph(AT91_PIO_PORTB, 19, 0); /* LCDD14 */
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at91_set_a_periph(AT91_PIO_PORTB, 20, 0); /* LCDD15 */
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at91_set_b_periph(AT91_PIO_PORTB, 23, 0); /* LCDD18 */
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at91_set_b_periph(AT91_PIO_PORTB, 24, 0); /* LCDD19 */
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at91_set_b_periph(AT91_PIO_PORTB, 25, 0); /* LCDD20 */
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at91_set_b_periph(AT91_PIO_PORTB, 26, 0); /* LCDD21 */
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at91_set_b_periph(AT91_PIO_PORTB, 27, 0); /* LCDD22 */
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at91_set_b_periph(AT91_PIO_PORTB, 28, 0); /* LCDD23 */
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writel(1 << 17, &pmc->scer); /* LCD controller Clock, AT91SAM9261 only */
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gd->fb_base = ATMEL_BASE_SRAM;
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}
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#ifdef CONFIG_LCD_INFO
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#include <nand.h>
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#include <version.h>
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extern flash_info_t flash_info[];
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void lcd_show_board_info(void)
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{
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ulong dram_size, nand_size, flash_size, dataflash_size;
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int i;
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char temp[32];
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lcd_printf ("%s\n", U_BOOT_VERSION);
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lcd_printf ("(C) 2009 Ronetix GmbH\n");
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lcd_printf ("support@ronetix.at\n");
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lcd_printf ("%s CPU at %s MHz",
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CONFIG_SYS_AT91_CPU_NAME,
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strmhz(temp, get_cpu_clk_rate()));
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dram_size = 0;
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for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
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dram_size += gd->bd->bi_dram[i].size;
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nand_size = 0;
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for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
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nand_size += nand_info[i].size;
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flash_size = 0;
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for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++)
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flash_size += flash_info[i].size;
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dataflash_size = 0;
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for (i = 0; i < CONFIG_SYS_MAX_DATAFLASH_BANKS; i++)
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dataflash_size += (unsigned int) dataflash_info[i].Device.pages_number *
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dataflash_info[i].Device.pages_size;
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lcd_printf ("%ld MB SDRAM, %ld MB NAND\n%ld MB NOR Flash\n"
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"%ld MB DataFlash\n",
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dram_size >> 20,
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nand_size >> 20,
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flash_size >> 20,
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dataflash_size >> 20);
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}
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#endif /* CONFIG_LCD_INFO */
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#endif /* CONFIG_LCD */
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int board_early_init_f(void)
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{
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struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
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/* Enable clocks for some PIOs */
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writel(1 << ATMEL_ID_PIOA |
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1 << ATMEL_ID_PIOC,
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&pmc->pcer);
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at91_seriald_hw_init();
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return 0;
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}
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int board_init(void)
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{
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/* arch number of PM9261-Board */
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gd->bd->bi_arch_number = MACH_TYPE_PM9261;
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/* adress of boot parameters */
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gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
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#ifdef CONFIG_CMD_NAND
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pm9261_nand_hw_init();
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#endif
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#ifdef CONFIG_HAS_DATAFLASH
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at91_spi0_hw_init(1 << 0);
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#endif
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#ifdef CONFIG_DRIVER_DM9000
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pm9261_dm9000_hw_init();
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#endif
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#ifdef CONFIG_LCD
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pm9261_lcd_hw_init();
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#endif
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return 0;
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}
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#ifdef CONFIG_DRIVER_DM9000
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int board_eth_init(bd_t *bis)
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{
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return dm9000_initialize(bis);
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}
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#endif
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int dram_init(void)
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{
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/* dram_init must store complete ramsize in gd->ram_size */
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gd->ram_size = get_ram_size((void *)PHYS_SDRAM,
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PHYS_SDRAM_SIZE);
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return 0;
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}
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void dram_init_banksize(void)
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{
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gd->bd->bi_dram[0].start = PHYS_SDRAM;
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gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
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}
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#ifdef CONFIG_RESET_PHY_R
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void reset_phy(void)
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{
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#ifdef CONFIG_DRIVER_DM9000
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/*
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* Initialize ethernet HW addr prior to starting Linux,
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* needed for nfsroot
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*/
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eth_init();
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#endif
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}
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#endif
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#ifdef CONFIG_DISPLAY_BOARDINFO
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int checkboard (void)
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{
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char buf[32];
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printf ("Board : Ronetix PM9261\n");
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printf ("Crystal frequency: %8s MHz\n",
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strmhz(buf, get_main_clk_rate()));
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printf ("CPU clock : %8s MHz\n",
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strmhz(buf, get_cpu_clk_rate()));
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printf ("Master clock : %8s MHz\n",
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strmhz(buf, get_mck_clk_rate()));
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return 0;
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}
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#endif
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