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https://github.com/brain-hackers/u-boot-brain
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76b3f195e9
ARM supported speeds and init value of core_pll for SDP1200
are programmed wrong as part for the device speed cleanups.
Fixing it here.
Thanks to "Vitaly Andrianov <vitalya@ti.com>" for bisecting this issue
Fixes: c37ed9f11b61 ("ARM: keystone2: Fix dev and arm speed detection")
Tested-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
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|---|---|---|
| .. | ||
| clock_defs.h | ||
| clock-k2e.h | ||
| clock-k2hk.h | ||
| clock-k2l.h | ||
| clock.h | ||
| ddr3.h | ||
| hardware-k2e.h | ||
| hardware-k2hk.h | ||
| hardware-k2l.h | ||
| hardware.h | ||
| i2c_defs.h | ||
| mon.h | ||
| msmc.h | ||
| psc_defs.h | ||
| xhci-keystone.h | ||