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https://github.com/brain-hackers/u-boot-brain
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3c8ae536ec
Move PCI_REG_ADDR and PCI_REG_DATA from arch/x86/lib/pci_type1.c to arch/x86/include/asm/pci.h, also define PCI_CFG_EN so that these macros can be used for pci configuration space access. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
51 lines
1.3 KiB
C
51 lines
1.3 KiB
C
/*
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* (C) Copyright 2002
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* Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/*
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* Support for type PCI configuration cycles.
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* based on pci_indirect.c
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <pci.h>
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#include <asm/pci.h>
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#define cfg_read(val, addr, op) (*val = op((int)(addr)))
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#define cfg_write(val, addr, op) op((val), (int)(addr))
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#define TYPE1_PCI_OP(rw, size, type, op, mask) \
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static int \
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type1_##rw##_config_##size(struct pci_controller *hose, \
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pci_dev_t dev, int offset, type val) \
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{ \
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outl(dev | (offset & 0xfc) | PCI_CFG_EN, (int)hose->cfg_addr); \
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cfg_##rw(val, hose->cfg_data + (offset & mask), op); \
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return 0; \
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}
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TYPE1_PCI_OP(read, byte, u8 *, inb, 3)
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TYPE1_PCI_OP(read, word, u16 *, inw, 2)
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TYPE1_PCI_OP(read, dword, u32 *, inl, 0)
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TYPE1_PCI_OP(write, byte, u8, outb, 3)
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TYPE1_PCI_OP(write, word, u16, outw, 2)
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TYPE1_PCI_OP(write, dword, u32, outl, 0)
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void pci_setup_type1(struct pci_controller *hose)
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{
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pci_set_ops(hose,
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type1_read_config_byte,
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type1_read_config_word,
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type1_read_config_dword,
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type1_write_config_byte,
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type1_write_config_word,
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type1_write_config_dword);
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hose->cfg_addr = (unsigned int *)PCI_REG_ADDR;
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hose->cfg_data = (unsigned char *)PCI_REG_DATA;
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}
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