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https://github.com/brain-hackers/u-boot-brain
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faa8323299
In the Quark SoC, some chipset commands are accomplished by utilizing the internal message network within the host bridge (D0:F0). Accesses to this network are accomplished by populating the message control register (MCR), Message Control Register eXtension (MCRX) and the message data register (MDR). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
78 lines
1.9 KiB
C
78 lines
1.9 KiB
C
/*
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* Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <pci.h>
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#include <asm/arch/device.h>
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#include <asm/arch/msg_port.h>
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void msg_port_setup(int op, int port, int reg)
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{
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pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_REG,
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(((op) << 24) | ((port) << 16) |
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(((reg) << 8) & 0xff00) | MSG_BYTE_ENABLE));
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}
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u32 msg_port_read(u8 port, u32 reg)
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{
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u32 value;
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pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_EXT_REG,
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reg & 0xffffff00);
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msg_port_setup(MSG_OP_READ, port, reg);
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pci_read_config_dword(QUARK_HOST_BRIDGE, MSG_DATA_REG, &value);
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return value;
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}
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void msg_port_write(u8 port, u32 reg, u32 value)
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{
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pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_DATA_REG, value);
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pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_EXT_REG,
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reg & 0xffffff00);
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msg_port_setup(MSG_OP_WRITE, port, reg);
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}
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u32 msg_port_alt_read(u8 port, u32 reg)
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{
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u32 value;
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pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_EXT_REG,
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reg & 0xffffff00);
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msg_port_setup(MSG_OP_ALT_READ, port, reg);
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pci_read_config_dword(QUARK_HOST_BRIDGE, MSG_DATA_REG, &value);
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return value;
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}
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void msg_port_alt_write(u8 port, u32 reg, u32 value)
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{
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pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_DATA_REG, value);
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pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_EXT_REG,
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reg & 0xffffff00);
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msg_port_setup(MSG_OP_ALT_WRITE, port, reg);
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}
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u32 msg_port_io_read(u8 port, u32 reg)
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{
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u32 value;
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pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_EXT_REG,
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reg & 0xffffff00);
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msg_port_setup(MSG_OP_IO_READ, port, reg);
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pci_read_config_dword(QUARK_HOST_BRIDGE, MSG_DATA_REG, &value);
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return value;
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}
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void msg_port_io_write(u8 port, u32 reg, u32 value)
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{
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pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_DATA_REG, value);
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pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_EXT_REG,
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reg & 0xffffff00);
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msg_port_setup(MSG_OP_IO_WRITE, port, reg);
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}
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