mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-23 19:39:44 +09:00
b41411954d
U-Boot has never cared about the type when we get max/min of two values, but Linux Kernel does. This commit gets min, max, min3, max3 macros synced with the kernel introducing type checks. Many of references of those macros must be fixed to suppress warnings. We have two options: - Use min, max, min3, max3 only when the arguments have the same type (or add casts to the arguments) - Use min_t/max_t instead with the appropriate type for the first argument Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Pavel Machek <pavel@denx.de> Acked-by: Lukasz Majewski <l.majewski@samsung.com> Tested-by: Lukasz Majewski <l.majewski@samsung.com> [trini: Fixup arch/blackfin/lib/string.c] Signed-off-by: Tom Rini <trini@ti.com>
83 lines
2.0 KiB
C
83 lines
2.0 KiB
C
/*
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* Copyright (C) 2005-2008 Atmel Corporation
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/clk.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/portmux.h>
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#include "sm.h"
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void clk_init(void)
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{
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uint32_t cksel;
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/* in case of soft resets, disable watchdog */
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sm_writel(WDT_CTRL, SM_BF(KEY, 0x55));
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sm_writel(WDT_CTRL, SM_BF(KEY, 0xaa));
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#ifdef CONFIG_PLL
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/* Initialize the PLL */
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sm_writel(PM_PLL0, (SM_BF(PLLCOUNT, CONFIG_SYS_PLL0_SUPPRESS_CYCLES)
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| SM_BF(PLLMUL, CONFIG_SYS_PLL0_MUL - 1)
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| SM_BF(PLLDIV, CONFIG_SYS_PLL0_DIV - 1)
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| SM_BF(PLLOPT, CONFIG_SYS_PLL0_OPT)
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| SM_BF(PLLOSC, 0)
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| SM_BIT(PLLEN)));
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/* Wait for lock */
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while (!(sm_readl(PM_ISR) & SM_BIT(LOCK0))) ;
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#endif
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/* Set up clocks for the CPU and all peripheral buses */
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cksel = 0;
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if (CONFIG_SYS_CLKDIV_CPU)
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cksel |= SM_BIT(CPUDIV) | SM_BF(CPUSEL, CONFIG_SYS_CLKDIV_CPU - 1);
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if (CONFIG_SYS_CLKDIV_HSB)
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cksel |= SM_BIT(HSBDIV) | SM_BF(HSBSEL, CONFIG_SYS_CLKDIV_HSB - 1);
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if (CONFIG_SYS_CLKDIV_PBA)
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cksel |= SM_BIT(PBADIV) | SM_BF(PBASEL, CONFIG_SYS_CLKDIV_PBA - 1);
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if (CONFIG_SYS_CLKDIV_PBB)
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cksel |= SM_BIT(PBBDIV) | SM_BF(PBBSEL, CONFIG_SYS_CLKDIV_PBB - 1);
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sm_writel(PM_CKSEL, cksel);
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#ifdef CONFIG_PLL
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/* Use PLL0 as main clock */
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sm_writel(PM_MCCTRL, SM_BIT(PLLSEL));
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#ifdef CONFIG_LCD
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/* Set up pixel clock for the LCDC */
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sm_writel(PM_GCCTRL(7), SM_BIT(PLLSEL) | SM_BIT(CEN));
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#endif
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#endif
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}
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unsigned long __gclk_set_rate(unsigned int id, enum gclk_parent parent,
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unsigned long rate, unsigned long parent_rate)
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{
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unsigned long divider;
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if (rate == 0 || parent_rate == 0) {
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sm_writel(PM_GCCTRL(id), 0);
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return 0;
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}
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divider = (parent_rate + rate / 2) / rate;
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if (divider <= 1) {
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sm_writel(PM_GCCTRL(id), parent | SM_BIT(CEN));
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rate = parent_rate;
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} else {
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divider = min(255UL, divider / 2 - 1);
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sm_writel(PM_GCCTRL(id), parent | SM_BIT(CEN) | SM_BIT(DIVEN)
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| SM_BF(DIV, divider));
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rate = parent_rate / (2 * (divider + 1));
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}
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return rate;
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}
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