mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-18 16:08:53 +09:00
263 lines
7.9 KiB
C
263 lines
7.9 KiB
C
/*
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* (C) Copyright 2005
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/processor.h>
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#include <command.h>
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#include "p3p440.h"
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DECLARE_GLOBAL_DATA_PTR;
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void set_led(int color)
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{
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switch (color) {
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case LED_OFF:
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out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_LED_GREEN & ~CFG_LED_RED);
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break;
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case LED_GREEN:
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out32(GPIO0_OR, (in32(GPIO0_OR) | CFG_LED_GREEN) & ~CFG_LED_RED);
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break;
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case LED_RED:
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out32(GPIO0_OR, (in32(GPIO0_OR) | CFG_LED_RED) & ~CFG_LED_GREEN);
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break;
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case LED_ORANGE:
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out32(GPIO0_OR, in32(GPIO0_OR) | CFG_LED_GREEN | CFG_LED_RED);
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break;
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}
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}
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static int is_monarch(void)
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{
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out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_GPIO_RDY);
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udelay(1000);
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if (in32(GPIO0_IR) & CFG_MONARCH_IO)
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return 0;
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else
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return 1;
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}
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static void wait_for_pci_ready(void)
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{
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/*
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* Configure EREADY_IO as input
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*/
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out32(GPIO0_TCR, in32(GPIO0_TCR) & ~CFG_EREADY_IO);
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udelay(1000);
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for (;;) {
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if (in32(GPIO0_IR) & CFG_EREADY_IO)
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return;
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}
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}
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int board_early_init_f(void)
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{
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uint reg;
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/*--------------------------------------------------------------------
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* Setup the external bus controller/chip selects
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*-------------------------------------------------------------------*/
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mtdcr(ebccfga, xbcfg);
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reg = mfdcr(ebccfgd);
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mtdcr(ebccfgd, reg | 0x04000000); /* Set ATC */
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/*--------------------------------------------------------------------
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* Setup pin multiplexing (GPIO/IRQ...)
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*-------------------------------------------------------------------*/
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mtdcr(cpc0_gpio, 0x03F01F80);
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out32(GPIO0_ODR, 0x00000000); /* no open drain pins */
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out32(GPIO0_TCR, CFG_GPIO_RDY | CFG_EREADY_IO | CFG_LED_RED | CFG_LED_GREEN);
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out32(GPIO0_OR, CFG_GPIO_RDY);
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/*--------------------------------------------------------------------
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* Setup the interrupt controller polarities, triggers, etc.
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*-------------------------------------------------------------------*/
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mtdcr(uic0sr, 0xffffffff); /* clear all */
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mtdcr(uic0er, 0x00000000); /* disable all */
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mtdcr(uic0cr, 0x00000001); /* UIC1 crit is critical */
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mtdcr(uic0pr, 0xfffffe13); /* per ref-board manual */
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mtdcr(uic0tr, 0x01c00008); /* per ref-board manual */
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mtdcr(uic0vr, 0x00000001); /* int31 highest, base=0x000 */
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mtdcr(uic0sr, 0xffffffff); /* clear all */
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mtdcr(uic1sr, 0xffffffff); /* clear all */
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mtdcr(uic1er, 0x00000000); /* disable all */
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mtdcr(uic1cr, 0x00000000); /* all non-critical */
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mtdcr(uic1pr, 0xffffe0ff); /* per ref-board manual */
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mtdcr(uic1tr, 0x00ffc000); /* per ref-board manual */
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mtdcr(uic1vr, 0x00000001); /* int31 highest, base=0x000 */
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mtdcr(uic1sr, 0xffffffff); /* clear all */
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return 0;
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}
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int checkboard(void)
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{
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char *s = getenv("serial#");
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printf("Board: P3P440");
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if (s != NULL) {
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puts(", serial# ");
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puts(s);
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}
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if (is_monarch()) {
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puts(", Monarch");
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} else {
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puts(", None-Monarch");
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}
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putc('\n');
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return (0);
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}
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int misc_init_r (void)
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{
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/*
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* Adjust flash start and offset to detected values
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*/
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gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
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gd->bd->bi_flashoffset = 0;
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/*
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* Check if only one FLASH bank is available
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*/
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if (gd->bd->bi_flashsize != CFG_MAX_FLASH_BANKS * (0 - CFG_FLASH0)) {
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mtebc(pb1cr, 0); /* disable cs */
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mtebc(pb1ap, 0);
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mtebc(pb2cr, 0); /* disable cs */
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mtebc(pb2ap, 0);
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mtebc(pb3cr, 0); /* disable cs */
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mtebc(pb3ap, 0);
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}
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return 0;
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}
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/*************************************************************************
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* pci_pre_init
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*
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* This routine is called just prior to registering the hose and gives
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* the board the opportunity to check things. Returning a value of zero
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* indicates that things are bad & PCI initialization should be aborted.
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*
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* Different boards may wish to customize the pci controller structure
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* (add regions, override default access routines, etc) or perform
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* certain pre-initialization actions.
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*
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************************************************************************/
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#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
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int pci_pre_init(struct pci_controller *hose)
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{
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unsigned long strap;
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/*--------------------------------------------------------------------------+
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* The P3P440 board is always configured as the host & requires the
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* PCI arbiter to be disabled because it's an PMC module.
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*--------------------------------------------------------------------------*/
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strap = mfdcr(cpc0_strp1);
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if (strap & 0x00100000) {
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printf("PCI: CPC0_STRP1[PAE] set.\n");
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return 0;
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}
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return 1;
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}
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#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
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/*************************************************************************
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* pci_target_init
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*
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* The bootstrap configuration provides default settings for the pci
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* inbound map (PIM). But the bootstrap config choices are limited and
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* may not be sufficient for a given board.
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*
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************************************************************************/
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#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
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void pci_target_init(struct pci_controller *hose)
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{
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/*--------------------------------------------------------------------------+
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* Disable everything
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*--------------------------------------------------------------------------*/
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out32r(PCIX0_PIM0SA, 0); /* disable */
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out32r(PCIX0_PIM1SA, 0); /* disable */
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out32r(PCIX0_PIM2SA, 0); /* disable */
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out32r(PCIX0_EROMBA, 0); /* disable expansion rom */
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/*--------------------------------------------------------------------------+
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* Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
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* options to not support sizes such as 128/256 MB.
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*--------------------------------------------------------------------------*/
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out32r(PCIX0_PIM0LAL, CFG_SDRAM_BASE);
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out32r(PCIX0_PIM0LAH, 0);
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out32r(PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1);
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out32r(PCIX0_BAR0, 0);
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/*--------------------------------------------------------------------------+
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* Program the board's subsystem id/vendor id
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*--------------------------------------------------------------------------*/
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out16r(PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID);
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out16r(PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID);
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out16r(PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY);
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}
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#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
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/*************************************************************************
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* is_pci_host
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*
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* This routine is called to determine if a pci scan should be
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* performed. With various hardware environments (especially cPCI and
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* PPMC) it's insufficient to depend on the state of the arbiter enable
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* bit in the strap register, or generic host/adapter assumptions.
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*
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* Rather than hard-code a bad assumption in the general 440 code, the
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* 440 pci code requires the board to decide at runtime.
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*
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* Return 0 for adapter mode, non-zero for host (monarch) mode.
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*
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*
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************************************************************************/
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#if defined(CONFIG_PCI)
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int is_pci_host(struct pci_controller *hose)
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{
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if (is_monarch()) {
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wait_for_pci_ready();
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return 1; /* return 1 for host controller */
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} else {
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return 0; /* return 0 for adapter controller */
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}
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}
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#endif /* defined(CONFIG_PCI) */
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