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https://github.com/brain-hackers/u-boot-brain
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526a50f8ec
In the linux kernel, non cacheable buffers are used. However in uboot since there are no APIs to allocate non cacheable memory, all the buffers should be flushed before using it. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
56 lines
1.4 KiB
C
56 lines
1.4 KiB
C
/**
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* io.h - DesignWare USB3 DRD IO Header
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*
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* Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com
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*
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* Authors: Felipe Balbi <balbi@ti.com>,
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* Sebastian Andrzej Siewior <bigeasy@linutronix.de>
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*
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* Taken from Linux Kernel v3.19-rc1 (drivers/usb/dwc3/io.h) and ported
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* to uboot.
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*
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* commit 2c4cbe6e5a : usb: dwc3: add tracepoints to aid debugging
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*
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* SPDX-License-Identifier: GPL-2.0
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*
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*/
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#ifndef __DRIVERS_USB_DWC3_IO_H
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#define __DRIVERS_USB_DWC3_IO_H
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#include <asm/io.h>
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#define CACHELINE_SIZE CONFIG_SYS_CACHELINE_SIZE
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static inline u32 dwc3_readl(void __iomem *base, u32 offset)
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{
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u32 offs = offset - DWC3_GLOBALS_REGS_START;
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u32 value;
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/*
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* We requested the mem region starting from the Globals address
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* space, see dwc3_probe in core.c.
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* However, the offsets are given starting from xHCI address space.
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*/
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value = readl(base + offs);
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return value;
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}
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static inline void dwc3_writel(void __iomem *base, u32 offset, u32 value)
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{
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u32 offs = offset - DWC3_GLOBALS_REGS_START;
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/*
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* We requested the mem region starting from the Globals address
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* space, see dwc3_probe in core.c.
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* However, the offsets are given starting from xHCI address space.
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*/
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writel(value, base + offs);
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}
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static inline void dwc3_flush_cache(int addr, int length)
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{
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flush_dcache_range(addr, addr + ROUND(length, CACHELINE_SIZE));
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}
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#endif /* __DRIVERS_USB_DWC3_IO_H */
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