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https://github.com/brain-hackers/u-boot-brain
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![Stefano Babic](/assets/img/avatar_default.png)
Change is consistent with other SOCs and it is in preparation for adding SOMs. SOC's related files are moved from cpu/ to mach-imx/<SOC>. This change is also coherent with the structure in kernel. Signed-off-by: Stefano Babic <sbabic@denx.de> CC: Fabio Estevam <fabio.estevam@nxp.com> CC: Akshay Bhat <akshaybhat@timesys.com> CC: Ken Lin <Ken.Lin@advantech.com.tw> CC: Marek Vasut <marek.vasut@gmail.com> CC: Heiko Schocher <hs@denx.de> CC: "Sébastien Szymanski" <sebastien.szymanski@armadeus.com> CC: Christian Gmeiner <christian.gmeiner@gmail.com> CC: Stefan Roese <sr@denx.de> CC: Patrick Bruenn <p.bruenn@beckhoff.com> CC: Troy Kisky <troy.kisky@boundarydevices.com> CC: Nikita Kiryanov <nikita@compulab.co.il> CC: Otavio Salvador <otavio@ossystems.com.br> CC: "Eric Bénard" <eric@eukrea.com> CC: Jagan Teki <jagan@amarulasolutions.com> CC: Ye Li <ye.li@nxp.com> CC: Peng Fan <peng.fan@nxp.com> CC: Adrian Alonso <adrian.alonso@nxp.com> CC: Alison Wang <b18965@freescale.com> CC: Tim Harvey <tharvey@gateworks.com> CC: Martin Donnelly <martin.donnelly@ge.com> CC: Marcin Niestroj <m.niestroj@grinn-global.com> CC: Lukasz Majewski <lukma@denx.de> CC: Adam Ford <aford173@gmail.com> CC: "Albert ARIBAUD (3ADEV)" <albert.aribaud@3adev.fr> CC: Boris Brezillon <boris.brezillon@free-electrons.com> CC: Soeren Moch <smoch@web.de> CC: Richard Hu <richard.hu@technexion.com> CC: Wig Cheng <wig.cheng@technexion.com> CC: Vanessa Maegima <vanessa.maegima@nxp.com> CC: Max Krummenacher <max.krummenacher@toradex.com> CC: Stefan Agner <stefan.agner@toradex.com> CC: Markus Niebel <Markus.Niebel@tq-group.com> CC: Breno Lima <breno.lima@nxp.com> CC: Francesco Montefoschi <francesco.montefoschi@udoo.org> CC: Jaehoon Chung <jh80.chung@samsung.com> CC: Scott Wood <oss@buserror.net> CC: Joe Hershberger <joe.hershberger@ni.com> CC: Anatolij Gustschin <agust@denx.de> CC: Simon Glass <sjg@chromium.org> CC: "Andrew F. Davis" <afd@ti.com> CC: "Łukasz Majewski" <l.majewski@samsung.com> CC: Patrice Chotard <patrice.chotard@st.com> CC: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> CC: Hans de Goede <hdegoede@redhat.com> CC: Masahiro Yamada <yamada.masahiro@socionext.com> CC: Stephen Warren <swarren@nvidia.com> CC: Andre Przywara <andre.przywara@arm.com> CC: "Álvaro Fernández Rojas" <noltari@gmail.com> CC: York Sun <york.sun@nxp.com> CC: Xiaoliang Yang <xiaoliang.yang@nxp.com> CC: Chen-Yu Tsai <wens@csie.org> CC: George McCollister <george.mccollister@gmail.com> CC: Sven Ebenfeld <sven.ebenfeld@gmail.com> CC: Filip Brozovic <fbrozovic@gmail.com> CC: Petr Kulhavy <brain@jikos.cz> CC: Eric Nelson <eric@nelint.com> CC: Bai Ping <ping.bai@nxp.com> CC: Anson Huang <Anson.Huang@nxp.com> CC: Sanchayan Maity <maitysanchayan@gmail.com> CC: Lokesh Vutla <lokeshvutla@ti.com> CC: Patrick Delaunay <patrick.delaunay@st.com> CC: Gary Bisson <gary.bisson@boundarydevices.com> CC: Alexander Graf <agraf@suse.de> CC: u-boot@lists.denx.de Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
73 lines
1.9 KiB
C
73 lines
1.9 KiB
C
/*
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* Copyright (C) 2016 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <command.h>
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/* Allow for arch specific config before we boot */
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static int __arch_auxiliary_core_up(u32 core_id, u32 boot_private_data)
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{
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/* please define platform specific arch_auxiliary_core_up() */
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return CMD_RET_FAILURE;
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}
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int arch_auxiliary_core_up(u32 core_id, u32 boot_private_data)
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__attribute__((weak, alias("__arch_auxiliary_core_up")));
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/* Allow for arch specific config before we boot */
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static int __arch_auxiliary_core_check_up(u32 core_id)
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{
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/* please define platform specific arch_auxiliary_core_check_up() */
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return 0;
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}
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int arch_auxiliary_core_check_up(u32 core_id)
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__attribute__((weak, alias("__arch_auxiliary_core_check_up")));
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/*
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* To i.MX6SX and i.MX7D, the image supported by bootaux needs
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* the reset vector at the head for the image, with SP and PC
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* as the first two words.
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*
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* Per the cortex-M reference manual, the reset vector of M4 needs
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* to exist at 0x0 (TCMUL). The PC and SP are the first two addresses
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* of that vector. So to boot M4, the A core must build the M4's reset
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* vector with getting the PC and SP from image and filling them to
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* TCMUL. When M4 is kicked, it will load the PC and SP by itself.
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* The TCMUL is mapped to (M4_BOOTROM_BASE_ADDR) at A core side for
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* accessing the M4 TCMUL.
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*/
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int do_bootaux(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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ulong addr;
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int ret, up;
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if (argc < 2)
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return CMD_RET_USAGE;
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up = arch_auxiliary_core_check_up(0);
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if (up) {
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printf("## Auxiliary core is already up\n");
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return CMD_RET_SUCCESS;
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}
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addr = simple_strtoul(argv[1], NULL, 16);
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printf("## Starting auxiliary core at 0x%08lX ...\n", addr);
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ret = arch_auxiliary_core_up(0, addr);
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if (ret)
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return CMD_RET_FAILURE;
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return CMD_RET_SUCCESS;
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}
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U_BOOT_CMD(
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bootaux, CONFIG_SYS_MAXARGS, 1, do_bootaux,
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"Start auxiliary core",
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""
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);
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