mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-09-19 11:13:24 +09:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
140 lines
5.3 KiB
C
140 lines
5.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2015-2016 Freescale Semiconductor, Inc.
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* Copyright 2017 NXP
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*/
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#ifndef _EMAC_H_
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#define _EMAC_H_
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#define EMAC_IEVENT_REG 0x004
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#define EMAC_IMASK_REG 0x008
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#define EMAC_R_DES_ACTIVE_REG 0x010
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#define EMAC_X_DES_ACTIVE_REG 0x014
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#define EMAC_ECNTRL_REG 0x024
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#define EMAC_MII_DATA_REG 0x040
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#define EMAC_MII_CTRL_REG 0x044
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#define EMAC_MIB_CTRL_STS_REG 0x064
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#define EMAC_RCNTRL_REG 0x084
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#define EMAC_TCNTRL_REG 0x0C4
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#define EMAC_PHY_ADDR_LOW 0x0E4
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#define EMAC_PHY_ADDR_HIGH 0x0E8
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#define EMAC_TFWR_STR_FWD 0x144
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#define EMAC_RX_SECTIOM_FULL 0x190
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#define EMAC_TX_SECTION_EMPTY 0x1A0
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#define EMAC_TRUNC_FL 0x1B0
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/* GEMAC definitions and settings */
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#define EMAC_PORT_0 0
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#define EMAC_PORT_1 1
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/* GEMAC Bit definitions */
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#define EMAC_IEVENT_HBERR BIT(31)
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#define EMAC_IEVENT_BABR BIT(30)
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#define EMAC_IEVENT_BABT BIT(29)
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#define EMAC_IEVENT_GRA BIT(28)
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#define EMAC_IEVENT_TXF BIT(27)
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#define EMAC_IEVENT_TXB BIT(26)
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#define EMAC_IEVENT_RXF BIT(25)
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#define EMAC_IEVENT_RXB BIT(24)
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#define EMAC_IEVENT_MII BIT(23)
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#define EMAC_IEVENT_EBERR BIT(22)
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#define EMAC_IEVENT_LC BIT(21)
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#define EMAC_IEVENT_RL BIT(20)
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#define EMAC_IEVENT_UN BIT(19)
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#define EMAC_IMASK_HBERR BIT(31)
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#define EMAC_IMASK_BABR BIT(30)
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#define EMAC_IMASKT_BABT BIT(29)
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#define EMAC_IMASK_GRA BIT(28)
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#define EMAC_IMASKT_TXF BIT(27)
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#define EMAC_IMASK_TXB BIT(26)
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#define EMAC_IMASKT_RXF BIT(25)
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#define EMAC_IMASK_RXB BIT(24)
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#define EMAC_IMASK_MII BIT(23)
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#define EMAC_IMASK_EBERR BIT(22)
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#define EMAC_IMASK_LC BIT(21)
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#define EMAC_IMASKT_RL BIT(20)
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#define EMAC_IMASK_UN BIT(19)
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#define EMAC_RCNTRL_MAX_FL_SHIFT 16
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#define EMAC_RCNTRL_LOOP BIT(0)
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#define EMAC_RCNTRL_DRT BIT(1)
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#define EMAC_RCNTRL_MII_MODE BIT(2)
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#define EMAC_RCNTRL_PROM BIT(3)
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#define EMAC_RCNTRL_BC_REJ BIT(4)
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#define EMAC_RCNTRL_FCE BIT(5)
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#define EMAC_RCNTRL_RGMII BIT(6)
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#define EMAC_RCNTRL_SGMII BIT(7)
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#define EMAC_RCNTRL_RMII BIT(8)
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#define EMAC_RCNTRL_RMII_10T BIT(9)
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#define EMAC_RCNTRL_CRC_FWD BIT(10)
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#define EMAC_TCNTRL_GTS BIT(0)
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#define EMAC_TCNTRL_HBC BIT(1)
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#define EMAC_TCNTRL_FDEN BIT(2)
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#define EMAC_TCNTRL_TFC_PAUSE BIT(3)
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#define EMAC_TCNTRL_RFC_PAUSE BIT(4)
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#define EMAC_ECNTRL_RESET BIT(0) /* reset the EMAC */
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#define EMAC_ECNTRL_ETHER_EN BIT(1) /* enable the EMAC */
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#define EMAC_ECNTRL_SPEED BIT(5)
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#define EMAC_ECNTRL_DBSWAP BIT(8)
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#define EMAC_X_WMRK_STRFWD BIT(8)
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#define EMAC_X_DES_ACTIVE_TDAR BIT(24)
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#define EMAC_R_DES_ACTIVE_RDAR BIT(24)
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#define EMAC_TFWR (0x4)
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#define EMAC_RX_SECTION_FULL_32 (0x5)
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#define EMAC_TRUNC_FL_16K (0x3FFF)
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#define EMAC_TX_SECTION_EMPTY_30 (0x30)
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#define EMAC_MIBC_NO_CLR_NO_DIS (0x0)
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/*
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* The possible operating speeds of the MAC, currently supporting 10, 100 and
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* 1000Mb modes.
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*/
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enum mac_speed {PFE_MAC_SPEED_10M, PFE_MAC_SPEED_100M, PFE_MAC_SPEED_1000M,
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PFE_MAC_SPEED_1000M_PCS};
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/* MII-related definitios */
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#define EMAC_MII_DATA_ST 0x40000000 /* Start of frame delimiter */
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#define EMAC_MII_DATA_OP_RD 0x20000000 /* Perform a read operation */
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#define EMAC_MII_DATA_OP_CL45_RD 0x30000000 /* Perform a read operation */
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#define EMAC_MII_DATA_OP_WR 0x10000000 /* Perform a write operation */
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#define EMAC_MII_DATA_OP_CL45_WR 0x10000000 /* Perform a write operation */
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#define EMAC_MII_DATA_PA_MSK 0x0f800000 /* PHY Address field mask */
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#define EMAC_MII_DATA_RA_MSK 0x007c0000 /* PHY Register field mask */
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#define EMAC_MII_DATA_TA 0x00020000 /* Turnaround */
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#define EMAC_MII_DATA_DATAMSK 0x0000ffff /* PHY data field */
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#define EMAC_MII_DATA_RA_SHIFT 18 /* MII Register address bits */
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#define EMAC_MII_DATA_RA_MASK 0x1F /* MII Register address mask */
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#define EMAC_MII_DATA_PA_SHIFT 23 /* MII PHY address bits */
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#define EMAC_MII_DATA_PA_MASK 0x1F /* MII PHY address mask */
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#define EMAC_MII_DATA_RA(v) ((v & EMAC_MII_DATA_RA_MASK) <<\
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EMAC_MII_DATA_RA_SHIFT)
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#define EMAC_MII_DATA_PA(v) ((v & EMAC_MII_DATA_RA_MASK) <<\
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EMAC_MII_DATA_PA_SHIFT)
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#define EMAC_MII_DATA(v) (v & 0xffff)
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#define EMAC_MII_SPEED_SHIFT 1
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#define EMAC_HOLDTIME_SHIFT 8
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#define EMAC_HOLDTIME_MASK 0x7
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#define EMAC_HOLDTIME(v) ((v & EMAC_HOLDTIME_MASK) << EMAC_HOLDTIME_SHIFT)
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/* Internal PHY Registers - SGMII */
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#define PHY_SGMII_CR_PHY_RESET 0x8000
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#define PHY_SGMII_CR_RESET_AN 0x0200
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#define PHY_SGMII_CR_DEF_VAL 0x1140
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#define PHY_SGMII_DEV_ABILITY_SGMII 0x4001
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#define PHY_SGMII_IF_MODE_AN 0x0002
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#define PHY_SGMII_IF_MODE_SGMII 0x0001
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#define PHY_SGMII_IF_MODE_SGMII_GBT 0x0008
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#define PHY_SGMII_ENABLE_AN 0x1000
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#endif /* _EMAC_H_ */
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