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![Wolfgang Denk](/assets/img/avatar_default.png)
Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
170 lines
4.3 KiB
C
170 lines
4.3 KiB
C
/*
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* Copyright (c) 2004 Picture Elements, Inc.
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* Stephen Williams (steve@icarus.com)
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/ppc4xx.h>
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#include <asm/processor.h>
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# define SDRAM_LEN 0x08000000
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/*
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* this is even after checkboard. It returns the size of the SDRAM
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* that we have installed. This function is called by board_init_f
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* in arch/powerpc/lib/board.c to initialize the memory and return what I
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* found.
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*/
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phys_size_t initdram (int board_type)
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{
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/* Configure the SDRAMS */
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/* disable memory controller */
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mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG);
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mtdcr (SDRAM0_CFGDATA, 0x00000000);
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udelay (500);
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/* Clear SDRAM0_BESR0 (Bus Error Syndrome Register) */
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mtdcr (SDRAM0_CFGADDR, SDRAM0_BESR0);
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mtdcr (SDRAM0_CFGDATA, 0xffffffff);
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/* Clear SDRAM0_BESR1 (Bus Error Syndrome Register) */
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mtdcr (SDRAM0_CFGADDR, SDRAM0_BESR1);
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mtdcr (SDRAM0_CFGDATA, 0xffffffff);
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/* Clear SDRAM0_ECCCFG (disable ECC) */
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mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCCFG);
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mtdcr (SDRAM0_CFGDATA, 0x00000000);
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/* Clear SDRAM0_ECCESR (ECC Error Syndrome Register) */
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mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCESR);
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mtdcr (SDRAM0_CFGDATA, 0xffffffff);
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/* Timing register: CASL=2, PTA=2, CTP=2, LDF=1, RFTA=5, RCD=2 */
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mtdcr (SDRAM0_CFGADDR, SDRAM0_TR);
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mtdcr (SDRAM0_CFGDATA, 0x010a4016);
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/* Memory Bank 0 Config == BA=0x00000000, SZ=64M, AM=3, BE=1 */
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mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);
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mtdcr (SDRAM0_CFGDATA, 0x00084001);
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/* Memory Bank 1 Config == BA=0x04000000, SZ=64M, AM=3, BE=1 */
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mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR);
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mtdcr (SDRAM0_CFGDATA, 0x04084001);
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/* Memory Bank 2 Config == BE=0 */
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mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR);
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mtdcr (SDRAM0_CFGDATA, 0x00000000);
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/* Memory Bank 3 Config == BE=0 */
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mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR);
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mtdcr (SDRAM0_CFGDATA, 0x00000000);
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/* refresh timer = 0x400 */
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mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR);
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mtdcr (SDRAM0_CFGDATA, 0x04000000);
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/* Power management idle timer set to the default. */
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mtdcr (SDRAM0_CFGADDR, SDRAM0_PMIT);
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mtdcr (SDRAM0_CFGDATA, 0x07c00000);
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udelay (500);
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/* Enable banks (DCE=1, BPRF=1, ECCDD=1, EMDUL=1) */
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mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG);
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mtdcr (SDRAM0_CFGDATA, 0x80e00000);
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return SDRAM_LEN;
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}
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/*
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* The U-Boot core, as part of the initialization to prepare for
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* loading the monitor into SDRAM, requests of this function that the
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* memory be tested. Return 0 if the memory tests OK.
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*/
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int testdram (void)
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{
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unsigned long idx;
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unsigned val;
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unsigned errors;
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volatile unsigned long *sdram;
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#ifdef DEBUG
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printf ("SDRAM Controller Registers --\n");
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mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG);
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val = mfdcr (SDRAM0_CFGDATA);
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printf (" SDRAM0_CFG : 0x%08x\n", val);
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mtdcr (SDRAM0_CFGADDR, 0x24);
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val = mfdcr (SDRAM0_CFGDATA);
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printf (" SDRAM0_STATUS: 0x%08x\n", val);
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mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);
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val = mfdcr (SDRAM0_CFGDATA);
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printf (" SDRAM0_B0CR : 0x%08x\n", val);
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mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR);
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val = mfdcr (SDRAM0_CFGDATA);
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printf (" SDRAM0_B1CR : 0x%08x\n", val);
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mtdcr (SDRAM0_CFGADDR, SDRAM0_TR);
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val = mfdcr (SDRAM0_CFGDATA);
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printf (" SDRAM0_TR : 0x%08x\n", val);
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mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR);
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val = mfdcr (SDRAM0_CFGDATA);
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printf (" SDRAM0_RTR : 0x%08x\n", val);
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#endif
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/* Wait for memory to be ready by testing MRSCMPbit
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bit. Really, there should already have been plenty of time,
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given it was started long ago. But, best to check. */
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for (idx = 0; idx < 1000000; idx += 1) {
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mtdcr (SDRAM0_CFGADDR, 0x24);
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val = mfdcr (SDRAM0_CFGDATA);
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if (val & 0x80000000)
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break;
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}
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if (!(val & 0x80000000)) {
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printf ("SDRAM ERROR: SDRAM0_STATUS never set!\n");
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return 1;
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}
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/* Start memory test. */
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printf ("test: %u MB - ", SDRAM_LEN / 1048576);
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sdram = (unsigned long *) CONFIG_SYS_SDRAM_BASE;
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printf ("write - ");
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for (idx = 2; idx < SDRAM_LEN / 4; idx += 2) {
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sdram[idx + 0] = idx;
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sdram[idx + 1] = ~idx;
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}
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printf ("read - ");
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errors = 0;
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for (idx = 2; idx < SDRAM_LEN / 4; idx += 2) {
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if (sdram[idx + 0] != idx)
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errors += 1;
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if (sdram[idx + 1] != ~idx)
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errors += 1;
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if (errors > 0)
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break;
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}
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if (errors > 0) {
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printf ("NOT OK\n");
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printf ("FIRST ERROR at %p: 0x%08lx:0x%08lx != 0x%08lx:0x%08lx\n",
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sdram + idx, sdram[idx + 0], sdram[idx + 1], idx, ~idx);
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return 1;
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}
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printf ("ok\n");
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return 0;
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}
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