mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-15 15:46:16 +09:00
a52ff334c5
Using changes in this patch we were able to reduce approx 4k size of u-boot-spl.bin image. Following is breif description of changes to reduce SPL size: 1. Changes in board/freescale/ls1046ardb/Makefile to remove compilation of eth.c and cpld.c in case of SPL build. 2. Changes in board/freescale/ls1046ardb/ls1046ardb.c to keep only ddr_init and board_early_init_f funcations in case of SPL build. 3. Changes in ls1046a_common.h & ls1046ardb.h to remove driver specific macros due to which static data was being compiled in case of SPL build. 4. Disable MMC driver from bieng compiled in case of SPL NAND build and NAND driver from bieng compiled in case of SPL MMC build. Signed-off-by: Vinitha Pillai <vinitha.pillai@nxp.com> Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
228 lines
6.4 KiB
C
228 lines
6.4 KiB
C
/*
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* Copyright 2016 Freescale Semiconductor
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __LS1046A_COMMON_H
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#define __LS1046A_COMMON_H
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/* SPL build */
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#ifdef CONFIG_SPL_BUILD
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#define SPL_NO_QBMAN
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#define SPL_NO_FMAN
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#define SPL_NO_ENV
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#define SPL_NO_MISC
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#define SPL_NO_QSPI
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#define SPL_NO_USB
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#define SPL_NO_SATA
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#endif
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#if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_NAND_BOOT))
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#define SPL_NO_MMC
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#endif
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#if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SD_BOOT))
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#define SPL_NO_IFC
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#endif
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#define CONFIG_REMAKE_ELF
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#define CONFIG_FSL_LAYERSCAPE
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#define CONFIG_MP
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#define CONFIG_GICV2
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#include <asm/arch/config.h>
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#include <asm/arch/stream_id_lsch2.h>
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/* Link Definitions */
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#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
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#define CONFIG_SUPPORT_RAW_INITRD
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#define CONFIG_SKIP_LOWLEVEL_INIT
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#define CONFIG_VERY_BIG_RAM
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#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
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#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
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#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
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#define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL
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#define CPU_RELEASE_ADDR secondary_boot_func
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/* Generic Timer Definitions */
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#define COUNTER_FREQUENCY 25000000 /* 25MHz */
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/* Size of malloc() pool */
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#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024)
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/* Serial Port */
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#define CONFIG_CONS_INDEX 1
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#define CONFIG_SYS_NS16550_SERIAL
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#define CONFIG_SYS_NS16550_REG_SIZE 1
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#define CONFIG_SYS_NS16550_CLK (get_serial_clock())
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#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
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/* SD boot SPL */
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#ifdef CONFIG_SD_BOOT
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#define CONFIG_SPL_FRAMEWORK
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#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
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#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
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#define CONFIG_SPL_LIBCOMMON_SUPPORT
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#define CONFIG_SPL_LIBGENERIC_SUPPORT
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#define CONFIG_SPL_ENV_SUPPORT
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#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
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#define CONFIG_SPL_WATCHDOG_SUPPORT
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#define CONFIG_SPL_I2C_SUPPORT
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#define CONFIG_SPL_SERIAL_SUPPORT
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#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
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#define CONFIG_SPL_MMC_SUPPORT
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#define CONFIG_SPL_TEXT_BASE 0x10000000
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#define CONFIG_SPL_MAX_SIZE 0x1f000 /* 124 KiB */
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#define CONFIG_SPL_STACK 0x10020000
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#define CONFIG_SPL_PAD_TO 0x21000 /* 132 KiB */
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#define CONFIG_SPL_BSS_START_ADDR 0x8f000000
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#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
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#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \
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CONFIG_SPL_BSS_MAX_SIZE)
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#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
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#define CONFIG_SYS_MONITOR_LEN 0xa0000
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#endif
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/* NAND SPL */
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#ifdef CONFIG_NAND_BOOT
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#define CONFIG_SPL_PBL_PAD
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#define CONFIG_SPL_FRAMEWORK
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#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
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#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
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#define CONFIG_SPL_LIBCOMMON_SUPPORT
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#define CONFIG_SPL_LIBGENERIC_SUPPORT
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#define CONFIG_SPL_ENV_SUPPORT
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#define CONFIG_SPL_WATCHDOG_SUPPORT
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#define CONFIG_SPL_I2C_SUPPORT
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#define CONFIG_SPL_SERIAL_SUPPORT
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#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
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#define CONFIG_SPL_NAND_SUPPORT
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#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
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#define CONFIG_SPL_TEXT_BASE 0x10000000
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#define CONFIG_SPL_MAX_SIZE 0x1d000 /* 116 KiB */
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#define CONFIG_SPL_STACK 0x1001f000
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#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
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#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
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#define CONFIG_SPL_BSS_START_ADDR 0x8f000000
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#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
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#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \
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CONFIG_SPL_BSS_MAX_SIZE)
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#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
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#define CONFIG_SYS_MONITOR_LEN 0xa0000
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#endif
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/* I2C */
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#define CONFIG_SYS_I2C
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#define CONFIG_SYS_I2C_MXC
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#define CONFIG_SYS_I2C_MXC_I2C1
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#define CONFIG_SYS_I2C_MXC_I2C2
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#define CONFIG_SYS_I2C_MXC_I2C3
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#define CONFIG_SYS_I2C_MXC_I2C4
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/* Command line configuration */
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#ifndef SPL_NO_ENV
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#define CONFIG_CMD_ENV
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#endif
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/* MMC */
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#ifndef SPL_NO_MMC
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#ifdef CONFIG_MMC
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#define CONFIG_FSL_ESDHC
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#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
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#endif
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#endif
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#ifndef SPL_NO_QBMAN
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#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
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#endif
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/* FMan ucode */
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#ifndef SPL_NO_FMAN
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#define CONFIG_SYS_DPAA_FMAN
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#ifdef CONFIG_SYS_DPAA_FMAN
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#define CONFIG_SYS_FM_MURAM_SIZE 0x60000
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#endif
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#ifdef CONFIG_SD_BOOT
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/*
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* PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
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* about 1MB (2048 blocks), Env is stored after the image, and the env size is
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* 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820).
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*/
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#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
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#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
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#elif defined(CONFIG_QSPI_BOOT)
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#define CONFIG_SYS_QE_FW_IN_SPIFLASH
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#define CONFIG_SYS_FMAN_FW_ADDR 0x40300000
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#define CONFIG_ENV_SPI_BUS 0
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#define CONFIG_ENV_SPI_CS 0
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#define CONFIG_ENV_SPI_MAX_HZ 1000000
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#define CONFIG_ENV_SPI_MODE 0x03
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#elif defined(CONFIG_NAND_BOOT)
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#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
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#define CONFIG_SYS_FMAN_FW_ADDR (6 * CONFIG_SYS_NAND_BLOCK_SIZE)
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#else
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#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
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#define CONFIG_SYS_FMAN_FW_ADDR 0x60300000
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#endif
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#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
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#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
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#endif
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/* Miscellaneous configurable options */
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#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
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#define CONFIG_HWCONFIG
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#define HWCONFIG_BUFFER_SIZE 128
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#ifndef SPL_NO_MISC
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/* Initial environment variables */
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"hwconfig=fsl_ddr:bank_intlv=auto\0" \
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"loadaddr=0x80100000\0" \
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"ramdisk_addr=0x800000\0" \
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"ramdisk_size=0x2000000\0" \
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"fdt_high=0xffffffffffffffff\0" \
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"initrd_high=0xffffffffffffffff\0" \
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"kernel_start=0x1000000\0" \
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"kernel_load=0xa0000000\0" \
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"kernel_size=0x2800000\0" \
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"console=ttyS0,115200\0" \
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MTDPARTS_DEFAULT "\0"
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#define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/ram0 " \
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"earlycon=uart8250,mmio,0x21c0500 " \
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MTDPARTS_DEFAULT
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#endif
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/* Monitor Command Prompt */
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#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
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sizeof(CONFIG_SYS_PROMPT) + 16)
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */
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#define CONFIG_SYS_LONGHELP
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#ifndef SPL_NO_MISC
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#define CONFIG_CMDLINE_EDITING 1
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#endif
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#define CONFIG_AUTO_COMPLETE
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#define CONFIG_SYS_MAXARGS 64 /* max command args */
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#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
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/* Hash command with SHA acceleration supported in hardware */
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#ifdef CONFIG_FSL_CAAM
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#define CONFIG_CMD_HASH
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#define CONFIG_SHA_HW_ACCEL
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#endif
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#endif /* __LS1046A_COMMON_H */
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