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https://github.com/brain-hackers/u-boot-brain
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![]() Added d-cache support for zynq_gem.c, Observed a difference of +0.8 MiB/s when downloading a file of size of 3007944Bytes. With d-cache OFF: ---------------- Filename 'uImage'. Load address: 0x800 Loading: ################################################################# ################################################################# ################################################################# ########## 1.3 MiB/s done Bytes transferred = 3007944 (2de5c8 hex) With d-cache ON: --------------- Filename 'uImage'. Load address: 0x800 Loading: ################################################################# ################################################################# ################################################################# ########## 2.1 MiB/s done Bytes transferred = 3007944 (2de5c8 hex) Changes on zynq_gem for d-cache support: - Tx and Rx buffers are cache-aligned - Updated logic for invalidating Rx buffers and flushing Tx buffers. - Tx and Rx BD's are allocated from non-cacheable region. (When BDs are cached, we don't see a consistent link) - Use TX BD status intead of txsr status checks. Signed-off-by: Srikanth Thokala <sthokal@xilinx.com> Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> |
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.. | ||
bios_emulator | ||
block | ||
bootcount | ||
crypto | ||
dfu | ||
dma | ||
fpga | ||
gpio | ||
hwmon | ||
i2c | ||
input | ||
misc | ||
mmc | ||
mtd | ||
net | ||
pci | ||
pcmcia | ||
power | ||
qe | ||
rtc | ||
serial | ||
sound | ||
spi | ||
tpm | ||
twserial | ||
usb | ||
video | ||
watchdog | ||
Makefile |