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https://github.com/brain-hackers/u-boot-brain
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![Tom Rini](/assets/img/avatar_default.png)
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
158 lines
3.9 KiB
C
158 lines
3.9 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/**
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* Copyright 2011 Freescale Semiconductor
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* Author: Mingkai Hu <Mingkai.hu@freescale.com>
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*
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* This file provides support for the board-specific CPLD used on some Freescale
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* reference boards.
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*
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* The following macros need to be defined:
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*
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* CPLD_BASE - The virtual address of the base of the CPLD register map
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*/
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#include <common.h>
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#include <command.h>
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#include <asm/io.h>
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#include "cpld.h"
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static u8 __cpld_read(unsigned int reg)
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{
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void *p = (void *)CPLD_BASE;
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return in_8(p + reg);
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}
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u8 cpld_read(unsigned int reg) __attribute__((weak, alias("__cpld_read")));
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static void __cpld_write(unsigned int reg, u8 value)
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{
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void *p = (void *)CPLD_BASE;
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out_8(p + reg, value);
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}
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void cpld_write(unsigned int reg, u8 value)
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__attribute__((weak, alias("__cpld_write")));
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/*
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* Reset the board. This honors the por_cfg registers.
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*/
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void __cpld_reset(void)
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{
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CPLD_WRITE(system_rst, 1);
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}
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void cpld_reset(void) __attribute__((weak, alias("__cpld_reset")));
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/**
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* Set the boot bank to the alternate bank
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*/
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void __cpld_set_altbank(void)
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{
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u8 reg5 = CPLD_READ(sw_ctl_on);
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CPLD_WRITE(sw_ctl_on, reg5 | CPLD_SWITCH_BANK_ENABLE);
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CPLD_WRITE(fbank_sel, 1);
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CPLD_WRITE(system_rst, 1);
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}
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void cpld_set_altbank(void)
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__attribute__((weak, alias("__cpld_set_altbank")));
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/**
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* Set the boot bank to the default bank
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*/
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void __cpld_set_defbank(void)
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{
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CPLD_WRITE(system_rst_default, 1);
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}
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void cpld_set_defbank(void)
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__attribute__((weak, alias("__cpld_set_defbank")));
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#ifdef DEBUG
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static void cpld_dump_regs(void)
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{
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printf("cpld_ver = 0x%02x\n", CPLD_READ(cpld_ver));
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printf("cpld_ver_sub = 0x%02x\n", CPLD_READ(cpld_ver_sub));
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printf("pcba_ver = 0x%02x\n", CPLD_READ(pcba_ver));
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printf("system_rst = 0x%02x\n", CPLD_READ(system_rst));
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printf("sw_ctl_on = 0x%02x\n", CPLD_READ(sw_ctl_on));
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printf("por_cfg = 0x%02x\n", CPLD_READ(por_cfg));
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printf("switch_strobe = 0x%02x\n", CPLD_READ(switch_strobe));
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printf("jtag_sel = 0x%02x\n", CPLD_READ(jtag_sel));
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printf("sdbank1_clk = 0x%02x\n", CPLD_READ(sdbank1_clk));
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printf("sdbank2_clk = 0x%02x\n", CPLD_READ(sdbank2_clk));
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printf("fbank_sel = 0x%02x\n", CPLD_READ(fbank_sel));
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printf("serdes_mux = 0x%02x\n", CPLD_READ(serdes_mux));
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printf("SW[2] = 0x%02x\n", in_8(&CPLD_SW(2)));
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putc('\n');
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}
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#endif
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int cpld_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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int rc = 0;
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if (argc <= 1)
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return cmd_usage(cmdtp);
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if (strcmp(argv[1], "reset") == 0) {
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if (strcmp(argv[2], "altbank") == 0)
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cpld_set_altbank();
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else
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cpld_set_defbank();
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} else if (strcmp(argv[1], "lane_mux") == 0) {
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u32 lane = simple_strtoul(argv[2], NULL, 16);
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u8 val = (u8)simple_strtoul(argv[3], NULL, 16);
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u8 reg = CPLD_READ(serdes_mux);
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switch (lane) {
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case 0x6:
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reg &= ~SERDES_MUX_LANE_6_MASK;
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reg |= val << SERDES_MUX_LANE_6_SHIFT;
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break;
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case 0xa:
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reg &= ~SERDES_MUX_LANE_A_MASK;
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reg |= val << SERDES_MUX_LANE_A_SHIFT;
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break;
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case 0xc:
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reg &= ~SERDES_MUX_LANE_C_MASK;
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reg |= val << SERDES_MUX_LANE_C_SHIFT;
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break;
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case 0xd:
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reg &= ~SERDES_MUX_LANE_D_MASK;
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reg |= val << SERDES_MUX_LANE_D_SHIFT;
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break;
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default:
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printf("Invalid value\n");
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break;
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}
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CPLD_WRITE(serdes_mux, reg);
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#ifdef DEBUG
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} else if (strcmp(argv[1], "dump") == 0) {
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cpld_dump_regs();
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#endif
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} else
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rc = cmd_usage(cmdtp);
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return rc;
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}
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U_BOOT_CMD(
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cpld_cmd, CONFIG_SYS_MAXARGS, 1, cpld_cmd,
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"Reset the board or pin mulexing selection using the CPLD sequencer",
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"reset - hard reset to default bank\n"
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"cpld_cmd reset altbank - reset to alternate bank\n"
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"cpld_cmd lane_mux <lane> <mux_value> - set multiplexed lane pin\n"
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" lane 6: 0 -> slot1\n"
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" 1 -> SGMII (Default)\n"
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" lane a: 0 -> slot2\n"
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" 1 -> AURORA (Default)\n"
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" lane c: 0 -> slot2\n"
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" 1 -> SATA0 (Default)\n"
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" lane d: 0 -> slot2\n"
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" 1 -> SATA1 (Default)\n"
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#ifdef DEBUG
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"cpld_cmd dump - display the CPLD registers\n"
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#endif
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);
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