mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-30 05:48:51 +09:00
a4bcd67c72
There's already an SoC-specific conditional in cpu.h to determine the PLLP rate. Define the CSITE clock rate inside the same conditional, so that we can remove a conditional from clock_enable_coresight(). This means one less place to update the code for new SoCs. Signed-off-by: Stephen Warren <swarren@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com> |
||
|---|---|---|
| .. | ||
| cpu | ||
| dts | ||
| imx-common | ||
| include/asm | ||
| lib | ||
| config.mk | ||