Alexey Brodkin a4a43fcf9c arc/cache: Flush & invalidate all caches right before enabling IOC ... According to ARC HS databook it is required to flush and disable caches prior programming IOC registers. Otherwise ongoing coherent memory operations may not observe the coherency protocols as expected. But since in ARC HS v2.1 there's no way to disable SLC (AKA L2 cache) we're doing our best flushing and invalidating it. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>		2016-06-13 14:38:05 +02:00
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cpu	arc: make sure _start is in the beginning of .text section	2015-04-10 18:45:34 +03:00
dts	axs103: add support of generic OHCI USB 1.1 controller	2015-12-21 23:29:04 +03:00
include/asm	arc: Add virt_to_phys() stub	2016-04-11 10:20:38 -07:00
lib	arc/cache: Flush & invalidate all caches right before enabling IOC	2016-06-13 14:38:05 +02:00
config.mk	arc: use more universal prefix for default CROSS_COMPILE	2015-05-13 13:44:25 +03:00
Kconfig	arc: cache - accommodate different L1 cache line lengths	2016-02-20 11:19:53 +03:00
Makefile	arc: introduce separate section for interrupt vector table	2015-01-15 22:38:42 +03:00