Tom Warren a482f32992 mmc: t210: Fix 'bad' SD-card clock when doing 400KHz card detect ... According to the HW team, for some reason the normal clock select code picks what appears to be a perfectly valid 375KHz SD card clock, based on the CAR clock source and SDMMC1 controller register settings (CAR = 408MHz PLLP0 divided by 68 for 6MHz, then a SD Clock Control register divisor of 16 = 375KHz). But the resulting SD card clock, as measured by the HW team, is 700KHz, which is out-of-spec. So the WAR is to use the values given in the TRM PLLP table to generate a 400KHz SD-clock (CAR clock of 24.7MHz, SD Clock Control divisor of 62) only for SDMMC1 on T210 when the requested clock is <= 400KHz. Note that as far as I can tell, the other requests for clocks in the Tegra MMC driver result in valid SD clocks. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>		2020-04-02 14:30:01 -07:00
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asm	mmc: t210: Fix 'bad' SD-card clock when doing 400KHz card detect	2020-04-02 14:30:01 -07:00
debug	SPDX: Convert all of our single license tags to Linux Kernel style	2018-05-07 09:34:12 -04:00