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https://github.com/brain-hackers/u-boot-brain
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83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
143 lines
4.0 KiB
C
143 lines
4.0 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Meson GXL Internal PHY Driver
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*
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* Copyright (C) 2015 Amlogic, Inc. All rights reserved.
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* Copyright (C) 2016 BayLibre, SAS. All rights reserved.
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* Author: Neil Armstrong <narmstrong@baylibre.com>
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*/
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#include <config.h>
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#include <common.h>
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#include <linux/bitops.h>
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#include <dm.h>
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#include <phy.h>
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/* This function is provided to cope with the possible failures of this phy
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* during aneg process. When aneg fails, the PHY reports that aneg is done
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* but the value found in MII_LPA is wrong:
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* - Early failures: MII_LPA is just 0x0001. if MII_EXPANSION reports that
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* the link partner (LP) supports aneg but the LP never acked our base
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* code word, it is likely that we never sent it to begin with.
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* - Late failures: MII_LPA is filled with a value which seems to make sense
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* but it actually is not what the LP is advertising. It seems that we
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* can detect this using a magic bit in the WOL bank (reg 12 - bit 12).
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* If this particular bit is not set when aneg is reported being done,
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* it means MII_LPA is likely to be wrong.
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*
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* In both case, forcing a restart of the aneg process solve the problem.
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* When this failure happens, the first retry is usually successful but,
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* in some cases, it may take up to 6 retries to get a decent result
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*/
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int meson_gxl_startup(struct phy_device *phydev)
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{
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unsigned int retries = 10;
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int ret, wol, lpa, exp;
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restart_aneg:
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ret = genphy_update_link(phydev);
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if (ret)
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return ret;
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if (phydev->autoneg == AUTONEG_ENABLE) {
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/* Need to access WOL bank, make sure the access is open */
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ret = phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0000);
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if (ret)
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return ret;
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ret = phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0400);
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if (ret)
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return ret;
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ret = phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0000);
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if (ret)
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return ret;
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ret = phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0400);
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if (ret)
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return ret;
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/* Request LPI_STATUS WOL register */
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ret = phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x8D80);
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if (ret)
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return ret;
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/* Read LPI_STATUS value */
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wol = phy_read(phydev, MDIO_DEVAD_NONE, 0x15);
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if (wol < 0)
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return wol;
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lpa = phy_read(phydev, MDIO_DEVAD_NONE, MII_LPA);
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if (lpa < 0)
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return lpa;
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exp = phy_read(phydev, MDIO_DEVAD_NONE, MII_EXPANSION);
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if (exp < 0)
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return exp;
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if (!(wol & BIT(12)) ||
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((exp & EXPANSION_NWAY) && !(lpa & LPA_LPACK))) {
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/* Looks like aneg failed after all */
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if (!retries) {
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printf("%s LPA corruption max attempts\n",
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phydev->dev->name);
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return -ETIMEDOUT;
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}
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printf("%s LPA corruption - aneg restart\n",
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phydev->dev->name);
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ret = genphy_restart_aneg(phydev);
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if (ret)
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return ret;
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--retries;
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goto restart_aneg;
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}
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}
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return genphy_parse_link(phydev);
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}
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static int meson_gxl_phy_config(struct phy_device *phydev)
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{
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/* Enable Analog and DSP register Bank access by */
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phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0000);
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phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0400);
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phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0000);
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phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0400);
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/* Write Analog register 23 */
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phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0x8E0D);
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phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x4417);
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/* Enable fractional PLL */
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phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0x0005);
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phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x5C1B);
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/* Program fraction FR_PLL_DIV1 */
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phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0x029A);
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phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x5C1D);
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/* Program fraction FR_PLL_DIV1 */
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phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0xAAAA);
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phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x5C1C);
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return genphy_config(phydev);
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}
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static struct phy_driver meson_gxl_phy_driver = {
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.name = "Meson GXL Internal PHY",
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.uid = 0x01814400,
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.mask = 0xfffffff0,
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.features = PHY_BASIC_FEATURES,
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.config = &meson_gxl_phy_config,
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.startup = &meson_gxl_startup,
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.shutdown = &genphy_shutdown,
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};
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int phy_meson_gxl_init(void)
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{
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phy_register(&meson_gxl_phy_driver);
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return 0;
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}
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