mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-09-12 15:53:21 +09:00
3f1af81b80
When boot from SRIO, slave's ucode can be stored in master's memory space, then slave can fetch the ucode image through SRIO interface. For the corenet platform, ucode is for Fman. Master needs to: 1. Put the slave's ucode image into it's own memory space. 2. Set an inbound SRIO window covered slave's ucode stored in master's memory space. Slave needs to: 1. Set a specific TLB entry in order to fetch ucode from master. 2. Set a LAW entry with the TargetID SRIO1 or SRIO2 for ucode. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
67 lines
2.2 KiB
C
67 lines
2.2 KiB
C
/*
|
|
* Copyright 2008-2011 Freescale Semiconductor, Inc.
|
|
*
|
|
* (C) Copyright 2000
|
|
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
|
*
|
|
* See file CREDITS for list of people who contributed to this
|
|
* project.
|
|
*
|
|
* This program is free software; you can redistribute it and/or
|
|
* modify it under the terms of the GNU General Public License as
|
|
* published by the Free Software Foundation; either version 2 of
|
|
* the License, or (at your option) any later version.
|
|
*
|
|
* This program is distributed in the hope that it will be useful,
|
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
* GNU General Public License for more details.
|
|
*
|
|
* You should have received a copy of the GNU General Public License
|
|
* along with this program; if not, write to the Free Software
|
|
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
|
* MA 02111-1307 USA
|
|
*/
|
|
|
|
#include <common.h>
|
|
#include <asm/fsl_law.h>
|
|
#include <asm/mmu.h>
|
|
|
|
struct law_entry law_table[] = {
|
|
SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
|
|
#ifdef CONFIG_SYS_BMAN_MEM_PHYS
|
|
SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_2M, LAW_TRGT_IF_BMAN),
|
|
#endif
|
|
#ifdef CONFIG_SYS_QMAN_MEM_PHYS
|
|
SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_2M, LAW_TRGT_IF_QMAN),
|
|
#endif
|
|
#ifdef PIXIS_BASE_PHYS
|
|
SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC),
|
|
#endif
|
|
#ifdef CPLD_BASE_PHYS
|
|
SET_LAW(CPLD_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC),
|
|
#endif
|
|
#ifdef CONFIG_SYS_DCSRBAR_PHYS
|
|
/* Limit DCSR to 32M to access NPC Trace Buffer */
|
|
SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR),
|
|
#endif
|
|
#ifdef CONFIG_SYS_NAND_BASE_PHYS
|
|
SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
|
|
#endif
|
|
#ifdef CONFIG_SRIOBOOT_SLAVE
|
|
#if defined(CONFIG_SRIOBOOT_SLAVE_PORT0)
|
|
SET_LAW(CONFIG_SYS_SRIOBOOT_SLAVE_ADDR_PHYS,
|
|
LAW_SIZE_1M, LAW_TRGT_IF_RIO_1),
|
|
SET_LAW(CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR_PHYS,
|
|
LAW_SIZE_1M, LAW_TRGT_IF_RIO_1),
|
|
#elif defined(CONFIG_SRIOBOOT_SLAVE_PORT1)
|
|
SET_LAW(CONFIG_SYS_SRIOBOOT_SLAVE_ADDR_PHYS,
|
|
LAW_SIZE_1M, LAW_TRGT_IF_RIO_2),
|
|
SET_LAW(CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR_PHYS,
|
|
LAW_SIZE_1M, LAW_TRGT_IF_RIO_2),
|
|
#endif
|
|
#endif
|
|
};
|
|
|
|
int num_law_entries = ARRAY_SIZE(law_table);
|