mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-09-10 14:53:26 +09:00
736fead8fd
All in-tree boards that use this controller have CONFIG_NET_MULTI added Also: - changed CONFIG_DRIVER_SMC911X* to CONFIG_SMC911X* - cleaned up line lengths - modified all boards that override weak function in this driver - added Signed-off-by: Ben Warren <biggerbadderben@gmail.com> Tested-by: Mike Frysinger <vapier@gentoo.org>
88 lines
2.3 KiB
C
88 lines
2.3 KiB
C
/*
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*
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* (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <netdev.h>
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#include <asm/arch/mx31.h>
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#include <asm/arch/mx31-regs.h>
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DECLARE_GLOBAL_DATA_PTR;
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int dram_init (void)
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{
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gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
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gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
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return 0;
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}
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int board_init (void)
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{
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__REG(CSCR_U(0)) = 0x0000cf03; /* CS0: Nor Flash */
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__REG(CSCR_L(0)) = 0xa0330d01;
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__REG(CSCR_A(0)) = 0x00220800;
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__REG(CSCR_U(4)) = 0x0000dcf6; /* CS4: Network Controller */
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__REG(CSCR_L(4)) = 0x444a4541;
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__REG(CSCR_A(4)) = 0x44443302;
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/* setup pins for UART1 */
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mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX);
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mx31_gpio_mux(MUX_TXD1__UART1_TXD_MUX);
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mx31_gpio_mux(MUX_RTS1__UART1_RTS_B);
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mx31_gpio_mux(MUX_CTS1__UART1_CTS_B);
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/* SPI2 */
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mx31_gpio_mux(MUX_CSPI2_SS2__CSPI2_SS2_B);
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mx31_gpio_mux(MUX_CSPI2_SCLK__CSPI2_CLK);
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mx31_gpio_mux(MUX_CSPI2_SPI_RDY__CSPI2_DATAREADY_B);
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mx31_gpio_mux(MUX_CSPI2_MOSI__CSPI2_MOSI);
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mx31_gpio_mux(MUX_CSPI2_MISO__CSPI2_MISO);
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mx31_gpio_mux(MUX_CSPI2_SS0__CSPI2_SS0_B);
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mx31_gpio_mux(MUX_CSPI2_SS1__CSPI2_SS1_B);
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/* start SPI2 clock */
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__REG(CCM_CGR2) = __REG(CCM_CGR2) | (3 << 4);
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gd->bd->bi_arch_number = MACH_TYPE_MX31LITE; /* board id for linux */
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gd->bd->bi_boot_params = (0x80000100); /* adress of boot parameters */
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return 0;
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}
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int checkboard (void)
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{
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printf("Board: i.MX31 Litekit\n");
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return 0;
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}
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int board_eth_init(bd_t *bis)
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{
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int rc = 0;
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#ifdef CONFIG_SMC911X
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rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
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#endif
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return rc;
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}
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