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![Tom Rini](/assets/img/avatar_default.png)
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
239 lines
5.5 KiB
C
239 lines
5.5 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2015 Freescale Semiconductor, Inc.
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*/
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#include <common.h>
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#include <fsl_ddr_sdram.h>
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#include <fsl_ddr_dimm_params.h>
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#include "ddr.h"
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#ifdef CONFIG_FSL_DEEP_SLEEP
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#include <fsl_sleep.h>
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#endif
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#include <asm/arch/clock.h>
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DECLARE_GLOBAL_DATA_PTR;
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void fsl_ddr_board_options(memctl_options_t *popts,
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dimm_params_t *pdimm,
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unsigned int ctrl_num)
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{
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const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
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ulong ddr_freq;
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if (ctrl_num > 1) {
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printf("Not supported controller number %d\n", ctrl_num);
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return;
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}
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if (!pdimm->n_ranks)
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return;
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pbsp = udimms[0];
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/* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr
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* freqency and n_banks specified in board_specific_parameters table.
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*/
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ddr_freq = get_ddr_freq(0) / 1000000;
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while (pbsp->datarate_mhz_high) {
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if (pbsp->n_ranks == pdimm->n_ranks) {
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if (ddr_freq <= pbsp->datarate_mhz_high) {
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popts->clk_adjust = pbsp->clk_adjust;
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popts->wrlvl_start = pbsp->wrlvl_start;
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popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
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popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
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popts->cpo_override = pbsp->cpo_override;
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popts->write_data_delay =
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pbsp->write_data_delay;
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goto found;
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}
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pbsp_highest = pbsp;
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}
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pbsp++;
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}
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if (pbsp_highest) {
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printf("Error: board specific timing not found for %lu MT/s\n",
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ddr_freq);
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printf("Trying to use the highest speed (%u) parameters\n",
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pbsp_highest->datarate_mhz_high);
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popts->clk_adjust = pbsp_highest->clk_adjust;
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popts->wrlvl_start = pbsp_highest->wrlvl_start;
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popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
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popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
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} else {
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panic("DIMM is not supported by this board");
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}
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found:
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debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n",
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pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb);
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/* force DDR bus width to 32 bits */
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popts->data_bus_width = 1;
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popts->otf_burst_chop_en = 0;
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popts->burst_length = DDR_BL8;
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/*
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* Factors to consider for half-strength driver enable:
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* - number of DIMMs installed
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*/
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popts->half_strength_driver_enable = 1;
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/*
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* Write leveling override
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*/
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popts->wrlvl_override = 1;
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popts->wrlvl_sample = 0xf;
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/*
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* Rtt and Rtt_WR override
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*/
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popts->rtt_override = 0;
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/* Enable ZQ calibration */
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popts->zq_en = 1;
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/* optimize cpo for erratum A-009942 */
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popts->cpo_sample = 0x46;
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popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm);
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popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) |
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DDR_CDR2_VREF_OVRD(70); /* Vref = 70% */
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}
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/* DDR model number: MT40A512M8HX-093E */
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#ifdef CONFIG_SYS_DDR_RAW_TIMING
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dimm_params_t ddr_raw_timing = {
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.n_ranks = 1,
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.rank_density = 2147483648u,
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.capacity = 2147483648u,
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.primary_sdram_width = 32,
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.ec_sdram_width = 0,
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.registered_dimm = 0,
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.mirrored_dimm = 0,
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.n_row_addr = 15,
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.n_col_addr = 10,
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.bank_addr_bits = 0,
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.bank_group_bits = 2,
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.edc_config = 0,
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.burst_lengths_bitmask = 0x0c,
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.tckmin_x_ps = 938,
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.tckmax_ps = 1500,
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.caslat_x = 0x000DFA00,
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.taa_ps = 13500,
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.trcd_ps = 13500,
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.trp_ps = 13500,
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.tras_ps = 33000,
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.trc_ps = 46500,
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.trfc1_ps = 260000,
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.trfc2_ps = 160000,
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.trfc4_ps = 110000,
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.tfaw_ps = 21000,
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.trrds_ps = 3700,
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.trrdl_ps = 5300,
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.tccdl_ps = 5355,
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.refresh_rate_ps = 7800000,
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.dq_mapping[0] = 0x0,
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.dq_mapping[1] = 0x0,
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.dq_mapping[2] = 0x0,
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.dq_mapping[3] = 0x0,
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.dq_mapping[4] = 0x0,
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.dq_mapping[5] = 0x0,
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.dq_mapping[6] = 0x0,
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.dq_mapping[7] = 0x0,
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.dq_mapping[8] = 0x0,
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.dq_mapping[9] = 0x0,
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.dq_mapping[10] = 0x0,
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.dq_mapping[11] = 0x0,
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.dq_mapping[12] = 0x0,
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.dq_mapping[13] = 0x0,
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.dq_mapping[14] = 0x0,
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.dq_mapping[15] = 0x0,
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.dq_mapping[16] = 0x0,
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.dq_mapping[17] = 0x0,
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.dq_mapping_ors = 0,
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};
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int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
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unsigned int controller_number,
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unsigned int dimm_number)
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{
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static const char dimm_model[] = "Fixed DDR on board";
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if (((controller_number == 0) && (dimm_number == 0)) ||
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((controller_number == 1) && (dimm_number == 0))) {
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memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
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memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
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memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
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}
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return 0;
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}
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#else
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phys_size_t fixed_sdram(void)
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{
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int i;
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char buf[32];
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fsl_ddr_cfg_regs_t ddr_cfg_regs;
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phys_size_t ddr_size;
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ulong ddr_freq, ddr_freq_mhz;
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ddr_freq = get_ddr_freq(0);
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ddr_freq_mhz = ddr_freq / 1000000;
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printf("Configuring DDR for %s MT/s data rate\n",
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strmhz(buf, ddr_freq));
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for (i = 0; fixed_ddr_parm_0[i].max_freq > 0; i++) {
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if ((ddr_freq_mhz > fixed_ddr_parm_0[i].min_freq) &&
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(ddr_freq_mhz <= fixed_ddr_parm_0[i].max_freq)) {
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memcpy(&ddr_cfg_regs,
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fixed_ddr_parm_0[i].ddr_settings,
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sizeof(ddr_cfg_regs));
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break;
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}
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}
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if (fixed_ddr_parm_0[i].max_freq == 0)
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panic("Unsupported DDR data rate %s MT/s data rate\n",
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strmhz(buf, ddr_freq));
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ddr_size = (phys_size_t)2048 * 1024 * 1024;
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fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0);
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return ddr_size;
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}
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#endif
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int fsl_initdram(void)
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{
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phys_size_t dram_size;
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#ifdef CONFIG_SYS_DDR_RAW_TIMING
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#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_SPL)
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puts("Initializing DDR....\n");
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dram_size = fsl_ddr_sdram();
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#else
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dram_size = fsl_ddr_sdram_size();
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#endif
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#else
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#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_SPL)
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puts("Initialzing DDR using fixed setting\n");
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dram_size = fixed_sdram();
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#else
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gd->ram_size = 0x80000000;
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return 0;
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#endif
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#endif
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erratum_a008850_post();
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#ifdef CONFIG_FSL_DEEP_SLEEP
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fsl_dp_ddr_restore();
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#endif
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gd->ram_size = dram_size;
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return 0;
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}
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