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![Priyanka Jain](/assets/img/avatar_default.png)
Update PBI command in pbi_cfg files to keep register bit to default reset value while configuring CPC as SRAM Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
37 lines
784 B
INI
37 lines
784 B
INI
#PBI commands
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#Software Workaround for errata A-007662 to train PCIe2 controller in Gen2 speed
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09250100 00000400
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09250108 00002000
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#Software Workaround for errata A-008007 to reset PVR register
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09000010 0000000b
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09000014 c0000000
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09000018 81d00017
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89020400 a1000000
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091380c0 000f0000
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89020400 00000000
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#Initialize CPC1
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09010000 00200400
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09138000 00000000
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091380c0 00000100
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#Configure CPC1 as 256KB SRAM
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09010100 00000000
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09010104 fffc0007
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09010f00 081e000d
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09010000 80000000
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#Configure LAW for CPC1
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09000cd0 00000000
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09000cd4 fffc0000
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09000cd8 81000011
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#Configure alternate space
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09000010 00000000
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09000014 ff000000
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09000018 81000000
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#Configure SPI controller
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09110000 80000403
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09110020 2d170008
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09110024 00100008
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09110028 00100008
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0911002c 00100008
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#Flush PBL data
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091380c0 000FFFFF
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