mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-25 19:38:52 +09:00
![Prabhakar Kushwaha](/assets/img/avatar_default.png)
The MDC generate by default value of MDIO_CLK_DIV is too high i.e. higher than 2.5 MHZ. It violates the IEEE specs. So Slow MDC clock to comply IEEE specs Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
31 lines
600 B
INI
31 lines
600 B
INI
#PBI commands
|
|
#Initialize CPC1
|
|
09010000 00200400
|
|
09138000 00000000
|
|
091380c0 00000100
|
|
#Configure CPC1 as 512KB SRAM
|
|
09010100 00000000
|
|
09010104 fff80009
|
|
09010f00 08000000
|
|
09010000 80000000
|
|
#Configure LAW for CPC1
|
|
09000d00 00000000
|
|
09000d04 fff80000
|
|
09000d08 81000012
|
|
#Configure alternate space
|
|
09000010 00000000
|
|
09000014 ff000000
|
|
09000018 81000000
|
|
#Configure SPI controller
|
|
09110000 80000403
|
|
09110020 2d170008
|
|
09110024 00100008
|
|
09110028 00100008
|
|
0911002c 00100008
|
|
#slowing down the MDC clock to make it <= 2.5 MHZ
|
|
094fc030 00008148
|
|
094fd030 00008148
|
|
#Flush PBL data
|
|
09138000 00000000
|
|
091380c0 00000000
|