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https://github.com/brain-hackers/u-boot-brain
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![]() When final MMU table is setup in DDR, TCR attributes must match those of the memroy for cacheability and shareability. Signed-off-by: Zhichun Hua <zhichun.hua@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com> |
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.. | ||
fsl-lsch3 | ||
zynqmp | ||
cache_v8.c | ||
cache.S | ||
config.mk | ||
cpu.c | ||
exceptions.S | ||
generic_timer.c | ||
Kconfig | ||
Makefile | ||
start.S | ||
tlb.S | ||
transition.S | ||
u-boot-spl.lds | ||
u-boot.lds |