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![Masahiro Yamada](/assets/img/avatar_default.png)
The pin data are implemented for old SoCs to specify the bit shift of the IECTRL register. They are not wortwhile given the required memory footprint. Delete all the pin data and enable all bits of the IECTRL register. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
303 lines
7.5 KiB
C
303 lines
7.5 KiB
C
/*
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* Copyright (C) 2015-2016 Socionext Inc.
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* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <dm.h>
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#include <linux/io.h>
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#include <linux/err.h>
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#include <linux/kernel.h>
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#include <linux/sizes.h>
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#include <dm/pinctrl.h>
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#include "pinctrl-uniphier.h"
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#define UNIPHIER_PINCTRL_PINMUX_BASE 0x1000
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#define UNIPHIER_PINCTRL_LOAD_PINMUX 0x1700
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#define UNIPHIER_PINCTRL_PUPDCTRL_BASE 0x1a00
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#define UNIPHIER_PINCTRL_IECTRL 0x1d00
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static const char *uniphier_pinctrl_dummy_name = "_dummy";
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static int uniphier_pinctrl_get_groups_count(struct udevice *dev)
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{
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struct uniphier_pinctrl_priv *priv = dev_get_priv(dev);
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return priv->socdata->groups_count;
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}
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static const char *uniphier_pinctrl_get_group_name(struct udevice *dev,
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unsigned selector)
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{
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struct uniphier_pinctrl_priv *priv = dev_get_priv(dev);
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if (!priv->socdata->groups[selector].name)
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return uniphier_pinctrl_dummy_name;
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return priv->socdata->groups[selector].name;
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}
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static int uniphier_pinmux_get_functions_count(struct udevice *dev)
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{
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struct uniphier_pinctrl_priv *priv = dev_get_priv(dev);
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return priv->socdata->functions_count;
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}
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static const char *uniphier_pinmux_get_function_name(struct udevice *dev,
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unsigned selector)
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{
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struct uniphier_pinctrl_priv *priv = dev_get_priv(dev);
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if (!priv->socdata->functions[selector])
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return uniphier_pinctrl_dummy_name;
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return priv->socdata->functions[selector];
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}
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static int uniphier_pinconf_input_enable_perpin(struct udevice *dev,
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unsigned int pin, int enable)
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{
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struct uniphier_pinctrl_priv *priv = dev_get_priv(dev);
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unsigned reg;
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u32 mask, tmp;
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reg = UNIPHIER_PINCTRL_IECTRL + pin / 32 * 4;
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mask = BIT(pin % 32);
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tmp = readl(priv->base + reg);
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if (enable)
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tmp |= mask;
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else
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tmp &= ~mask;
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writel(tmp, priv->base + reg);
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return 0;
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}
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static int uniphier_pinconf_input_enable_legacy(struct udevice *dev,
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unsigned int pin, int enable)
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{
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struct uniphier_pinctrl_priv *priv = dev_get_priv(dev);
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/*
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* Multiple pins share one input enable, per-pin disabling is
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* impossible.
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*/
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if (!enable)
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return -EINVAL;
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/* Set all bits instead of having a bunch of pin data */
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writel(U32_MAX, priv->base + UNIPHIER_PINCTRL_IECTRL);
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return 0;
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}
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static int uniphier_pinconf_input_enable(struct udevice *dev,
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unsigned int pin, int enable)
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{
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struct uniphier_pinctrl_priv *priv = dev_get_priv(dev);
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if (priv->socdata->caps & UNIPHIER_PINCTRL_CAPS_PERPIN_IECTRL)
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return uniphier_pinconf_input_enable_perpin(dev, pin, enable);
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else
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return uniphier_pinconf_input_enable_legacy(dev, pin, enable);
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}
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#if CONFIG_IS_ENABLED(PINCONF)
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static const struct pinconf_param uniphier_pinconf_params[] = {
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{ "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 },
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{ "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 1 },
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{ "bias-pull-down", PIN_CONFIG_BIAS_PULL_DOWN, 1 },
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{ "bias-pull-pin-default", PIN_CONFIG_BIAS_PULL_PIN_DEFAULT, 1 },
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{ "input-enable", PIN_CONFIG_INPUT_ENABLE, 1 },
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{ "input-disable", PIN_CONFIG_INPUT_ENABLE, 0 },
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};
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static int uniphier_pinconf_bias_set(struct udevice *dev, unsigned int pin,
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unsigned int param, unsigned int arg)
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{
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struct uniphier_pinctrl_priv *priv = dev_get_priv(dev);
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unsigned int enable = 1;
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unsigned int reg;
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u32 mask, tmp;
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if (!(priv->socdata->caps & UNIPHIER_PINCTRL_CAPS_PUPD_SIMPLE))
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return -ENOTSUPP;
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switch (param) {
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case PIN_CONFIG_BIAS_DISABLE:
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enable = 0;
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break;
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case PIN_CONFIG_BIAS_PULL_UP:
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case PIN_CONFIG_BIAS_PULL_DOWN:
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if (arg == 0) /* total bias is not supported */
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return -EINVAL;
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break;
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case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
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if (arg == 0) /* configuration ignored */
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return 0;
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default:
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BUG();
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}
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reg = UNIPHIER_PINCTRL_PUPDCTRL_BASE + pin / 32 * 4;
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mask = BIT(pin % 32);
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tmp = readl(priv->base + reg);
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if (enable)
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tmp |= mask;
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else
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tmp &= ~mask;
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writel(tmp, priv->base + reg);
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return 0;
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}
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static int uniphier_pinconf_set_one(struct udevice *dev, unsigned int pin,
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unsigned int param, unsigned int arg)
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{
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int ret;
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switch (param) {
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case PIN_CONFIG_BIAS_DISABLE:
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case PIN_CONFIG_BIAS_PULL_UP:
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case PIN_CONFIG_BIAS_PULL_DOWN:
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case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
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ret = uniphier_pinconf_bias_set(dev, pin, param, arg);
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break;
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case PIN_CONFIG_INPUT_ENABLE:
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ret = uniphier_pinconf_input_enable(dev, pin, arg);
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break;
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default:
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printf("unsupported configuration parameter %u\n", param);
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return -EINVAL;
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}
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return ret;
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}
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static int uniphier_pinconf_group_set(struct udevice *dev,
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unsigned int group_selector,
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unsigned int param, unsigned int arg)
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{
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struct uniphier_pinctrl_priv *priv = dev_get_priv(dev);
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const struct uniphier_pinctrl_group *grp =
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&priv->socdata->groups[group_selector];
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int i, ret;
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for (i = 0; i < grp->num_pins; i++) {
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ret = uniphier_pinconf_set_one(dev, grp->pins[i], param, arg);
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if (ret)
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return ret;
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}
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return 0;
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}
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#endif /* CONFIG_IS_ENABLED(PINCONF) */
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static void uniphier_pinmux_set_one(struct udevice *dev, unsigned pin,
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int muxval)
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{
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struct uniphier_pinctrl_priv *priv = dev_get_priv(dev);
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unsigned reg, reg_end, shift, mask;
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unsigned mux_bits = 8;
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unsigned reg_stride = 4;
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bool load_pinctrl = false;
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u32 tmp;
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/* some pins need input-enabling */
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uniphier_pinconf_input_enable(dev, pin, 1);
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if (muxval < 0)
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return; /* dedicated pin; nothing to do for pin-mux */
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if (priv->socdata->caps & UNIPHIER_PINCTRL_CAPS_MUX_4BIT)
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mux_bits = 4;
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if (priv->socdata->caps & UNIPHIER_PINCTRL_CAPS_DBGMUX_SEPARATE) {
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/*
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* Mode offset bit
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* Normal 4 * n shift+3:shift
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* Debug 4 * n shift+7:shift+4
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*/
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mux_bits /= 2;
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reg_stride = 8;
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load_pinctrl = true;
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}
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reg = UNIPHIER_PINCTRL_PINMUX_BASE + pin * mux_bits / 32 * reg_stride;
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reg_end = reg + reg_stride;
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shift = pin * mux_bits % 32;
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mask = (1U << mux_bits) - 1;
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/*
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* If reg_stride is greater than 4, the MSB of each pinsel shall be
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* stored in the offset+4.
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*/
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for (; reg < reg_end; reg += 4) {
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tmp = readl(priv->base + reg);
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tmp &= ~(mask << shift);
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tmp |= (mask & muxval) << shift;
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writel(tmp, priv->base + reg);
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muxval >>= mux_bits;
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}
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if (load_pinctrl)
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writel(1, priv->base + UNIPHIER_PINCTRL_LOAD_PINMUX);
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}
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static int uniphier_pinmux_group_set(struct udevice *dev,
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unsigned group_selector,
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unsigned func_selector)
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{
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struct uniphier_pinctrl_priv *priv = dev_get_priv(dev);
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const struct uniphier_pinctrl_group *grp =
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&priv->socdata->groups[group_selector];
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int i;
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for (i = 0; i < grp->num_pins; i++)
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uniphier_pinmux_set_one(dev, grp->pins[i], grp->muxvals[i]);
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return 0;
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}
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const struct pinctrl_ops uniphier_pinctrl_ops = {
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.get_groups_count = uniphier_pinctrl_get_groups_count,
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.get_group_name = uniphier_pinctrl_get_group_name,
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.get_functions_count = uniphier_pinmux_get_functions_count,
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.get_function_name = uniphier_pinmux_get_function_name,
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.pinmux_group_set = uniphier_pinmux_group_set,
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#if CONFIG_IS_ENABLED(PINCONF)
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.pinconf_num_params = ARRAY_SIZE(uniphier_pinconf_params),
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.pinconf_params = uniphier_pinconf_params,
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.pinconf_group_set = uniphier_pinconf_group_set,
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#endif
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.set_state = pinctrl_generic_set_state,
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};
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int uniphier_pinctrl_probe(struct udevice *dev,
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struct uniphier_pinctrl_socdata *socdata)
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{
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struct uniphier_pinctrl_priv *priv = dev_get_priv(dev);
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fdt_addr_t addr;
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addr = devfdt_get_addr(dev->parent);
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if (addr == FDT_ADDR_T_NONE)
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return -EINVAL;
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priv->base = devm_ioremap(dev, addr, SZ_4K);
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if (!priv->base)
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return -ENOMEM;
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priv->socdata = socdata;
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return 0;
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}
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