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![Philipp Tomsich](/assets/img/avatar_default.png)
With the new dev_read functions available, we can convert the rockchip architecture-specific drivers and common drivers used by these devices over to the dev_read family of calls. This change covers the pinctrl drivers for the Rockchip devices. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
184 lines
4.6 KiB
C
184 lines
4.6 KiB
C
/*
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* (C) Copyright 2016 Rockchip Electronics Co., Ltd
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* Author: Andy Yan <andy.yan@rock-chips.com>
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <dm.h>
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#include <errno.h>
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#include <syscon.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/grf_rv1108.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/periph.h>
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#include <dm/pinctrl.h>
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DECLARE_GLOBAL_DATA_PTR;
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struct rv1108_pinctrl_priv {
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struct rv1108_grf *grf;
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};
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static void pinctrl_rv1108_uart_config(struct rv1108_grf *grf, int uart_id)
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{
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switch (uart_id) {
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case PERIPH_ID_UART0:
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rk_clrsetreg(&grf->gpio3a_iomux,
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GPIO3A6_MASK | GPIO3A5_MASK,
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GPIO3A6_UART1_SOUT << GPIO3A6_SHIFT |
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GPIO3A5_UART1_SIN << GPIO3A5_SHIFT);
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break;
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case PERIPH_ID_UART1:
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rk_clrsetreg(&grf->gpio1d_iomux,
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GPIO1D3_MASK | GPIO1D2_MASK | GPIO1D1_MASK |
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GPIO1D0_MASK,
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GPIO1D3_UART0_SOUT << GPIO1D3_SHIFT |
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GPIO1D2_UART0_SIN << GPIO1D2_SHIFT |
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GPIO1D1_UART0_RTSN << GPIO1D1_SHIFT |
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GPIO1D0_UART0_CTSN << GPIO1D0_SHIFT);
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break;
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case PERIPH_ID_UART2:
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rk_clrsetreg(&grf->gpio2d_iomux,
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GPIO2D2_MASK | GPIO2D1_MASK,
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GPIO2D2_UART2_SOUT_M0 << GPIO2D2_SHIFT |
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GPIO2D1_UART2_SIN_M0 << GPIO2D1_SHIFT);
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break;
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}
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}
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static void pinctrl_rv1108_gmac_config(struct rv1108_grf *grf, int func)
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{
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rk_clrsetreg(&grf->gpio1b_iomux,
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GPIO1B7_MASK | GPIO1B6_MASK | GPIO1B5_MASK |
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GPIO1B4_MASK | GPIO1B3_MASK | GPIO1B2_MASK,
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GPIO1B7_GMAC_RXDV << GPIO1B7_SHIFT |
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GPIO1B6_GMAC_RXD1 << GPIO1B6_SHIFT |
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GPIO1B5_GMAC_RXD0 << GPIO1B5_SHIFT |
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GPIO1B4_GMAC_TXEN << GPIO1B4_SHIFT |
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GPIO1B3_GMAC_TXD1 << GPIO1B3_SHIFT |
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GPIO1B2_GMAC_TXD0 << GPIO1B2_SHIFT);
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rk_clrsetreg(&grf->gpio1c_iomux,
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GPIO1C5_MASK | GPIO1C4_MASK |
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GPIO1C3_MASK | GPIO1C2_MASK,
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GPIO1C5_GMAC_CLK << GPIO1C5_SHIFT |
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GPIO1C4_GMAC_MDC << GPIO1C4_SHIFT |
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GPIO1C3_GMAC_MDIO << GPIO1C3_SHIFT |
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GPIO1C2_GMAC_RXER << GPIO1C2_SHIFT);
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writel(0xffff57f5, &grf->gpio1b_drv);
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}
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static void pinctrl_rv1108_sfc_config(struct rv1108_grf *grf)
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{
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rk_clrsetreg(&grf->gpio2a_iomux, GPIO2A3_MASK | GPIO2A2_MASK |
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GPIO2A1_MASK | GPIO2A0_MASK,
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GPIO2A3_SFC_HOLD_IO3 << GPIO2A3_SHIFT |
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GPIO2A2_SFC_WP_IO2 << GPIO2A2_SHIFT |
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GPIO2A1_SFC_SO_IO1 << GPIO2A1_SHIFT |
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GPIO2A0_SFC_SI_IO0 << GPIO2A0_SHIFT);
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rk_clrsetreg(&grf->gpio2b_iomux, GPIO2B7_MASK | GPIO2B4_MASK,
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GPIO2B7_SFC_CLK << GPIO2B7_SHIFT |
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GPIO2B4_SFC_CSN0 << GPIO2B4_SHIFT);
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}
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static int rv1108_pinctrl_request(struct udevice *dev, int func, int flags)
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{
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struct rv1108_pinctrl_priv *priv = dev_get_priv(dev);
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switch (func) {
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case PERIPH_ID_UART0:
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case PERIPH_ID_UART1:
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case PERIPH_ID_UART2:
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pinctrl_rv1108_uart_config(priv->grf, func);
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break;
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case PERIPH_ID_GMAC:
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pinctrl_rv1108_gmac_config(priv->grf, func);
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case PERIPH_ID_SFC:
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pinctrl_rv1108_sfc_config(priv->grf);
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default:
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return -EINVAL;
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}
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return 0;
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}
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static int rv1108_pinctrl_get_periph_id(struct udevice *dev,
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struct udevice *periph)
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{
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u32 cell[3];
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int ret;
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ret = dev_read_u32_array(periph, "interrupts", cell, ARRAY_SIZE(cell));
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if (ret < 0)
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return -EINVAL;
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switch (cell[1]) {
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case 11:
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return PERIPH_ID_SDCARD;
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case 13:
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return PERIPH_ID_EMMC;
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case 19:
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return PERIPH_ID_GMAC;
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case 30:
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return PERIPH_ID_I2C0;
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case 31:
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return PERIPH_ID_I2C1;
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case 32:
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return PERIPH_ID_I2C2;
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case 39:
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return PERIPH_ID_PWM0;
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case 44:
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return PERIPH_ID_UART0;
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case 45:
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return PERIPH_ID_UART1;
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case 46:
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return PERIPH_ID_UART2;
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case 56:
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return PERIPH_ID_SFC;
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}
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return -ENOENT;
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}
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static int rv1108_pinctrl_set_state_simple(struct udevice *dev,
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struct udevice *periph)
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{
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int func;
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func = rv1108_pinctrl_get_periph_id(dev, periph);
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if (func < 0)
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return func;
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return rv1108_pinctrl_request(dev, func, 0);
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}
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static struct pinctrl_ops rv1108_pinctrl_ops = {
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.set_state_simple = rv1108_pinctrl_set_state_simple,
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.request = rv1108_pinctrl_request,
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.get_periph_id = rv1108_pinctrl_get_periph_id,
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};
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static int rv1108_pinctrl_probe(struct udevice *dev)
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{
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struct rv1108_pinctrl_priv *priv = dev_get_priv(dev);
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priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
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return 0;
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}
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static const struct udevice_id rv1108_pinctrl_ids[] = {
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{.compatible = "rockchip,rv1108-pinctrl" },
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{ }
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};
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U_BOOT_DRIVER(pinctrl_rv1108) = {
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.name = "pinctrl_rv1108",
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.id = UCLASS_PINCTRL,
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.of_match = rv1108_pinctrl_ids,
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.priv_auto_alloc_size = sizeof(struct rv1108_pinctrl_priv),
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.ops = &rv1108_pinctrl_ops,
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.bind = dm_scan_fdt_dev,
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.probe = rv1108_pinctrl_probe,
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};
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