mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-22 01:48:52 +09:00
![Konstantin Porotchkin](/assets/img/avatar_default.png)
Add a DM port of Marvell pin control driver. The A8K SoC family contains several silicone dies interconnected in a single package. Every die is normally equipped with its own pin controller unit. There are 2 pin controllers in A70x0 SoC and 3 in A80x0 SoC. Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Simon Glass <sjg@chromium.org> Cc: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Neta Zur Hershkovits <neta@marvell.com> Cc: Omri Itach <omrii@marvell.com> Cc: Igal Liberman <igall@marvell.com> Cc: Haim Boot <hayim@marvell.com> Cc: Hanna Hawa <hannah@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
32 lines
736 B
C
32 lines
736 B
C
/*
|
|
* Copyright (C) 2016 Marvell International Ltd.
|
|
*
|
|
* SPDX-License-Identifier: GPL-2.0
|
|
* https://spdx.org/licenses
|
|
*/
|
|
|
|
#ifndef __PINCTRL_MVEBU_H_
|
|
#define __PINCTRL_MVEBU_H_
|
|
|
|
#define MVEBU_MAX_PINCTL_BANKS 4
|
|
#define MVEBU_MAX_PINS_PER_BANK 100
|
|
#define MVEBU_MAX_FUNC 0xF
|
|
|
|
/*
|
|
* struct mvebu_pin_bank_data: mvebu-pinctrl bank data
|
|
* @base_reg: controller base address for this bank
|
|
* @pin_cnt: number of pins included in this bank
|
|
* @max_func: maximum configurable function value for pins in this bank
|
|
* @reg_direction:
|
|
* @bank_name: the pin's bank name
|
|
*/
|
|
struct mvebu_pinctrl_priv {
|
|
void *base_reg;
|
|
uint pin_cnt;
|
|
uint max_func;
|
|
int reg_direction;
|
|
const char *bank_name;
|
|
};
|
|
|
|
#endif /* __PINCTRL_MVEBU_H_ */
|