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![Beniamino Galvani](/assets/img/avatar_default.png)
This commit adds GPIO support to the Amlogic Meson pin controller driver, based on code from Linux kernel. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Beniamino Galvani <b.galvani@gmail.com>
343 lines
8.1 KiB
C
343 lines
8.1 KiB
C
/*
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* (C) Copyright 2016 - Beniamino Galvani <b.galvani@gmail.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <dm.h>
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#include <dm/device-internal.h>
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#include <dm/lists.h>
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#include <dm/pinctrl.h>
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#include <fdt_support.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/sizes.h>
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#include <asm/gpio.h>
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#include "pinctrl-meson.h"
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DECLARE_GLOBAL_DATA_PTR;
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static const char *meson_pinctrl_dummy_name = "_dummy";
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static int meson_pinctrl_get_groups_count(struct udevice *dev)
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{
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struct meson_pinctrl *priv = dev_get_priv(dev);
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return priv->data->num_groups;
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}
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static const char *meson_pinctrl_get_group_name(struct udevice *dev,
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unsigned selector)
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{
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struct meson_pinctrl *priv = dev_get_priv(dev);
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if (!priv->data->groups[selector].name)
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return meson_pinctrl_dummy_name;
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return priv->data->groups[selector].name;
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}
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static int meson_pinmux_get_functions_count(struct udevice *dev)
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{
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struct meson_pinctrl *priv = dev_get_priv(dev);
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return priv->data->num_funcs;
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}
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static const char *meson_pinmux_get_function_name(struct udevice *dev,
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unsigned selector)
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{
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struct meson_pinctrl *priv = dev_get_priv(dev);
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return priv->data->funcs[selector].name;
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}
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static void meson_pinmux_disable_other_groups(struct meson_pinctrl *priv,
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unsigned int pin, int sel_group)
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{
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struct meson_pmx_group *group;
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void __iomem *addr;
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int i, j;
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for (i = 0; i < priv->data->num_groups; i++) {
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group = &priv->data->groups[i];
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if (group->is_gpio || i == sel_group)
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continue;
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for (j = 0; j < group->num_pins; j++) {
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if (group->pins[j] == pin) {
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/* We have found a group using the pin */
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debug("pinmux: disabling %s\n", group->name);
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addr = priv->reg_mux + group->reg * 4;
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writel(readl(addr) & ~BIT(group->bit), addr);
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}
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}
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}
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}
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static int meson_pinmux_group_set(struct udevice *dev,
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unsigned group_selector,
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unsigned func_selector)
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{
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struct meson_pinctrl *priv = dev_get_priv(dev);
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const struct meson_pmx_group *group;
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const struct meson_pmx_func *func;
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void __iomem *addr;
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int i;
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group = &priv->data->groups[group_selector];
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func = &priv->data->funcs[func_selector];
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debug("pinmux: set group %s func %s\n", group->name, func->name);
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/*
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* Disable groups using the same pins.
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* The selected group is not disabled to avoid glitches.
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*/
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for (i = 0; i < group->num_pins; i++) {
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meson_pinmux_disable_other_groups(priv,
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group->pins[i],
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group_selector);
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}
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/* Function 0 (GPIO) doesn't need any additional setting */
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if (func_selector) {
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addr = priv->reg_mux + group->reg * 4;
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writel(readl(addr) | BIT(group->bit), addr);
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}
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return 0;
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}
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const struct pinctrl_ops meson_pinctrl_ops = {
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.get_groups_count = meson_pinctrl_get_groups_count,
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.get_group_name = meson_pinctrl_get_group_name,
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.get_functions_count = meson_pinmux_get_functions_count,
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.get_function_name = meson_pinmux_get_function_name,
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.pinmux_group_set = meson_pinmux_group_set,
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.set_state = pinctrl_generic_set_state,
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};
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static int meson_gpio_calc_reg_and_bit(struct udevice *dev, unsigned int offset,
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enum meson_reg_type reg_type,
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unsigned int *reg, unsigned int *bit)
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{
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struct meson_pinctrl *priv = dev_get_priv(dev->parent);
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struct meson_bank *bank = NULL;
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struct meson_reg_desc *desc;
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unsigned int pin;
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int i;
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pin = priv->data->pin_base + offset;
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for (i = 0; i < priv->data->num_banks; i++) {
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if (pin >= priv->data->banks[i].first &&
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pin <= priv->data->banks[i].last) {
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bank = &priv->data->banks[i];
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break;
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}
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}
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if (!bank)
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return -EINVAL;
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desc = &bank->regs[reg_type];
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*reg = desc->reg * 4;
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*bit = desc->bit + pin - bank->first;
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return 0;
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}
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static int meson_gpio_get(struct udevice *dev, unsigned int offset)
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{
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struct meson_pinctrl *priv = dev_get_priv(dev->parent);
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unsigned int reg, bit;
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int ret;
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ret = meson_gpio_calc_reg_and_bit(dev, offset, REG_IN, ®, &bit);
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if (ret)
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return ret;
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return !!(readl(priv->reg_gpio + reg) & BIT(bit));
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}
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static int meson_gpio_set(struct udevice *dev, unsigned int offset, int value)
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{
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struct meson_pinctrl *priv = dev_get_priv(dev->parent);
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unsigned int reg, bit;
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int ret;
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ret = meson_gpio_calc_reg_and_bit(dev, offset, REG_OUT, ®, &bit);
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if (ret)
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return ret;
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clrsetbits_le32(priv->reg_gpio + reg, BIT(bit), value ? BIT(bit) : 0);
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return 0;
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}
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static int meson_gpio_get_direction(struct udevice *dev, unsigned int offset)
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{
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struct meson_pinctrl *priv = dev_get_priv(dev->parent);
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unsigned int reg, bit, val;
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int ret;
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ret = meson_gpio_calc_reg_and_bit(dev, offset, REG_DIR, ®, &bit);
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if (ret)
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return ret;
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val = readl(priv->reg_gpio + reg);
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return (val & BIT(bit)) ? GPIOF_INPUT : GPIOF_OUTPUT;
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}
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static int meson_gpio_direction_input(struct udevice *dev, unsigned int offset)
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{
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struct meson_pinctrl *priv = dev_get_priv(dev->parent);
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unsigned int reg, bit;
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int ret;
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ret = meson_gpio_calc_reg_and_bit(dev, offset, REG_DIR, ®, &bit);
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if (ret)
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return ret;
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clrsetbits_le32(priv->reg_gpio + reg, BIT(bit), 1);
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return 0;
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}
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static int meson_gpio_direction_output(struct udevice *dev,
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unsigned int offset, int value)
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{
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struct meson_pinctrl *priv = dev_get_priv(dev->parent);
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unsigned int reg, bit;
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int ret;
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ret = meson_gpio_calc_reg_and_bit(dev, offset, REG_DIR, ®, &bit);
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if (ret)
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return ret;
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clrsetbits_le32(priv->reg_gpio + reg, BIT(bit), 0);
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ret = meson_gpio_calc_reg_and_bit(dev, offset, REG_OUT, ®, &bit);
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if (ret)
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return ret;
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clrsetbits_le32(priv->reg_gpio + reg, BIT(bit), value ? BIT(bit) : 0);
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return 0;
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}
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static int meson_gpio_probe(struct udevice *dev)
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{
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struct meson_pinctrl *priv = dev_get_priv(dev->parent);
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struct gpio_dev_priv *uc_priv;
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uc_priv = dev_get_uclass_priv(dev);
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uc_priv->bank_name = priv->data->name;
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uc_priv->gpio_count = priv->data->num_pins;
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return 0;
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}
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static const struct dm_gpio_ops meson_gpio_ops = {
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.set_value = meson_gpio_set,
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.get_value = meson_gpio_get,
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.get_function = meson_gpio_get_direction,
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.direction_input = meson_gpio_direction_input,
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.direction_output = meson_gpio_direction_output,
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};
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static struct driver meson_gpio_driver = {
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.name = "meson-gpio",
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.id = UCLASS_GPIO,
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.probe = meson_gpio_probe,
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.ops = &meson_gpio_ops,
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};
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static fdt_addr_t parse_address(int offset, const char *name, int na, int ns)
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{
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int index, len = 0;
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const fdt32_t *reg;
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index = fdt_stringlist_search(gd->fdt_blob, offset, "reg-names", name);
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if (index < 0)
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return FDT_ADDR_T_NONE;
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reg = fdt_getprop(gd->fdt_blob, offset, "reg", &len);
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if (!reg || (len <= (index * sizeof(fdt32_t) * (na + ns))))
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return FDT_ADDR_T_NONE;
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reg += index * (na + ns);
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return fdt_translate_address((void *)gd->fdt_blob, offset, reg);
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}
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int meson_pinctrl_probe(struct udevice *dev)
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{
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struct meson_pinctrl *priv = dev_get_priv(dev);
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struct uclass_driver *drv;
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struct udevice *gpio_dev;
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fdt_addr_t addr;
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int node, gpio = -1, len;
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int na, ns;
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char *name;
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na = fdt_address_cells(gd->fdt_blob, dev_of_offset(dev->parent));
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if (na < 1) {
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debug("bad #address-cells\n");
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return -EINVAL;
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}
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ns = fdt_size_cells(gd->fdt_blob, dev_of_offset(dev->parent));
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if (ns < 1) {
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debug("bad #size-cells\n");
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return -EINVAL;
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}
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fdt_for_each_subnode(node, gd->fdt_blob, dev_of_offset(dev)) {
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if (fdt_getprop(gd->fdt_blob, node, "gpio-controller", &len)) {
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gpio = node;
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break;
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}
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}
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if (!gpio) {
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debug("gpio node not found\n");
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return -EINVAL;
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}
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addr = parse_address(gpio, "mux", na, ns);
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if (addr == FDT_ADDR_T_NONE) {
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debug("mux address not found\n");
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return -EINVAL;
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}
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priv->reg_mux = (void __iomem *)addr;
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addr = parse_address(gpio, "gpio", na, ns);
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if (addr == FDT_ADDR_T_NONE) {
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debug("gpio address not found\n");
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return -EINVAL;
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}
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priv->reg_gpio = (void __iomem *)addr;
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priv->data = (struct meson_pinctrl_data *)dev_get_driver_data(dev);
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/* Lookup GPIO driver */
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drv = lists_uclass_lookup(UCLASS_GPIO);
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if (!drv) {
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puts("Cannot find GPIO driver\n");
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return -ENOENT;
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}
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name = calloc(1, 32);
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sprintf(name, "meson-gpio");
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/* Create child device UCLASS_GPIO and bind it */
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device_bind(dev, &meson_gpio_driver, name, NULL, gpio, &gpio_dev);
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dev_set_of_offset(gpio_dev, gpio);
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return 0;
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}
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