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https://github.com/brain-hackers/u-boot-brain
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c72f4d4c2e
- Initialize PLLs (SPL initializes only DPLL to save the precious SPL memory footprint) - Adjust CPLL/MPLL to the final tape-out frequency - Set the Cortex-A53 clock to the maximum frequency since it is running at 500MHz (SPLL/4) on startup Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
33 lines
1.2 KiB
Makefile
33 lines
1.2 KiB
Makefile
#
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# SPDX-License-Identifier: GPL-2.0+
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#
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ifdef CONFIG_SPL_BUILD
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obj-$(CONFIG_ARCH_UNIPHIER_SLD3) += early-clk-ld4.o dpll-sld3.o
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obj-$(CONFIG_ARCH_UNIPHIER_LD4) += early-clk-ld4.o dpll-ld4.o
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obj-$(CONFIG_ARCH_UNIPHIER_PRO4) += early-clk-ld4.o dpll-pro4.o
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obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += early-clk-ld4.o dpll-sld8.o
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obj-$(CONFIG_ARCH_UNIPHIER_PRO5) += early-clk-pro5.o
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obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += early-clk-pxs2.o
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obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += early-clk-pxs2.o
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obj-$(CONFIG_ARCH_UNIPHIER_LD11) += early-clk-ld11.o dpll-ld11.o
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obj-$(CONFIG_ARCH_UNIPHIER_LD20) += early-clk-ld20.o dpll-ld20.o
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else
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obj-$(CONFIG_ARCH_UNIPHIER_SLD3) += clk-ld4.o pll-sld3.o dpll-tail.o
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obj-$(CONFIG_ARCH_UNIPHIER_LD4) += clk-ld4.o pll-ld4.o dpll-tail.o
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obj-$(CONFIG_ARCH_UNIPHIER_PRO4) += clk-pro4.o pll-pro4.o dpll-tail.o
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obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += clk-ld4.o pll-ld4.o dpll-tail.o
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obj-$(CONFIG_ARCH_UNIPHIER_PRO5) += clk-pro5.o
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obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += clk-pxs2.o
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obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += clk-pxs2.o
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obj-$(CONFIG_ARCH_UNIPHIER_LD11) += clk-ld11.o pll-ld11.o
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obj-$(CONFIG_ARCH_UNIPHIER_LD20) += clk-ld20.o pll-ld20.o
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endif
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obj-$(CONFIG_ARCH_UNIPHIER_LD11) += pll-base-ld20.o
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obj-$(CONFIG_ARCH_UNIPHIER_LD20) += pll-base-ld20.o
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