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https://github.com/brain-hackers/u-boot-brain
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604aa9d30b
The PLL for the UART was not set, and relied on previous initializtion made by LK. add the appropriate initialization. Signed-off-by: Ramon Fried <ramon.fried@gmail.com>
38 lines
1.0 KiB
C
38 lines
1.0 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Qualcomm APQ8096 sysmap
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*
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* (C) Copyright 2017 Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
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*/
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#ifndef _MACH_SYSMAP_APQ8096_H
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#define _MACH_SYSMAP_APQ8096_H
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#define TLMM_BASE_ADDR (0x1010000)
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/* Strength (sdc1) */
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#define SDC1_HDRV_PULL_CTL_REG (TLMM_BASE_ADDR + 0x0012D000)
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/* Clocks: (from CLK_CTL_BASE) */
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#define GPLL0_STATUS (0x0000)
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#define APCS_GPLL_ENA_VOTE (0x52000)
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#define APCS_CLOCK_BRANCH_ENA_VOTE (0x52004)
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#define SDCC2_BCR (0x14000) /* block reset */
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#define SDCC2_APPS_CBCR (0x14004) /* branch control */
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#define SDCC2_AHB_CBCR (0x14008)
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#define SDCC2_CMD_RCGR (0x14010)
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#define SDCC2_CFG_RCGR (0x14014)
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#define SDCC2_M (0x14018)
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#define SDCC2_N (0x1401C)
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#define SDCC2_D (0x14020)
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#define BLSP2_AHB_CBCR (0x25004)
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#define BLSP2_UART2_APPS_CBCR (0x29004)
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#define BLSP2_UART2_APPS_CMD_RCGR (0x2900C)
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#define BLSP2_UART2_APPS_CFG_RCGR (0x29010)
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#define BLSP2_UART2_APPS_M (0x29014)
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#define BLSP2_UART2_APPS_N (0x29018)
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#define BLSP2_UART2_APPS_D (0x2901C)
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#endif
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