mirror of
https://github.com/brain-hackers/u-boot-brain
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83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
240 lines
8.4 KiB
C
240 lines
8.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2009 Jens Scharsig (js_at_ng@scharsoft.de)
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*/
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#ifndef AT91_MATRIX_H
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#define AT91_MATRIX_H
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#ifdef __ASSEMBLY__
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#if defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9G20)
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#define AT91_ASM_MATRIX_CSA0 (ATMEL_BASE_MATRIX + 0x11C)
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#elif defined(CONFIG_AT91SAM9261)
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#define AT91_ASM_MATRIX_CSA0 (ATMEL_BASE_MATRIX + 0x30)
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#elif defined(CONFIG_AT91SAM9263)
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#define AT91_ASM_MATRIX_CSA0 (ATMEL_BASE_MATRIX + 0x120)
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#elif defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45)
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#define AT91_ASM_MATRIX_CSA0 (ATMEL_BASE_MATRIX + 0x128)
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#else
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#error AT91_ASM_MATRIX_CSA0 is not definied for current CPU
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#endif
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#define AT91_ASM_MATRIX_MCFG ATMEL_BASE_MATRIX
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#else
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#if defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9G20)
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#define AT91_MATRIX_MASTERS 6
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#define AT91_MATRIX_SLAVES 5
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#elif defined(CONFIG_AT91SAM9261)
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#define AT91_MATRIX_MASTERS 1
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#define AT91_MATRIX_SLAVES 5
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#elif defined(CONFIG_AT91SAM9263)
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#define AT91_MATRIX_MASTERS 9
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#define AT91_MATRIX_SLAVES 7
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#elif defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45)
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#define AT91_MATRIX_MASTERS 11
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#define AT91_MATRIX_SLAVES 8
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#else
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#error CPU not supported. Please update at91_matrix.h
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#endif
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typedef struct at91_priority {
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u32 a;
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u32 b;
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} at91_priority_t;
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typedef struct at91_matrix {
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u32 mcfg[AT91_MATRIX_MASTERS];
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#if defined(CONFIG_AT91SAM9261)
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u32 scfg[AT91_MATRIX_SLAVES];
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u32 res61_1[3];
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u32 tcr;
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u32 res61_2[2];
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u32 csa;
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u32 pucr;
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u32 res61_3[114];
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#else
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u32 reserve1[16 - AT91_MATRIX_MASTERS];
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u32 scfg[AT91_MATRIX_SLAVES];
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u32 reserve2[16 - AT91_MATRIX_SLAVES];
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at91_priority_t pr[AT91_MATRIX_SLAVES];
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u32 reserve3[32 - (2 * AT91_MATRIX_SLAVES)];
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u32 mrcr; /* 0x100 Master Remap Control */
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u32 reserve4[3];
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#if defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45)
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u32 ccr[52]; /* 0x110 - 0x1E0 Chip Configuration */
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u32 womr; /* 0x1E4 Write Protect Mode */
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u32 wpsr; /* 0x1E8 Write Protect Status */
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u32 resg45_1[10];
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#elif defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9G20)
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u32 res60_1[3];
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u32 csa;
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u32 res60_2[56];
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#elif defined(CONFIG_AT91SAM9263)
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u32 res63_1;
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u32 tcmr;
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u32 res63_2[2];
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u32 csa[2];
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u32 res63_3[54];
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#else
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u32 reserve5[60];
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#endif
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#endif
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} at91_matrix_t;
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#endif /* __ASSEMBLY__ */
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#define AT91_MATRIX_CSA_DBPUC 0x00000100
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#define AT91_MATRIX_CSA_VDDIOMSEL_1_8V 0x00000000
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#define AT91_MATRIX_CSA_VDDIOMSEL_3_3V 0x00010000
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#define AT91_MATRIX_CSA_EBI_CS1A 0x00000002
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#define AT91_MATRIX_CSA_EBI_CS3A 0x00000008
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#define AT91_MATRIX_CSA_EBI_CS4A 0x00000010
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#define AT91_MATRIX_CSA_EBI_CS5A 0x00000020
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#define AT91_MATRIX_CSA_EBI1_CS2A 0x00000008
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#if defined CONFIG_AT91SAM9261
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/* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
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#define AT91_MATRIX_MCFG_RCB0 (1 << 0)
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/* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
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#define AT91_MATRIX_MCFG_RCB1 (1 << 1)
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#endif
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/* Undefined Length Burst Type */
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#if defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9263) || \
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defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45)
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#define AT91_MATRIX_MCFG_ULBT_INFINITE 0x00000000
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#define AT91_MATRIX_MCFG_ULBT_SINGLE 0x00000001
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#define AT91_MATRIX_MCFG_ULBT_FOUR 0x00000002
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#define AT91_MATRIX_MCFG_ULBT_EIGHT 0x00000003
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#define AT91_MATRIX_MCFG_ULBT_SIXTEEN 0x00000004
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#endif
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#if defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45)
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#define AT91_MATRIX_MCFG_ULBT_THIRTYTWO 0x00000005
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#define AT91_MATRIX_MCFG_ULBT_SIXTYFOUR 0x00000006
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#define AT91_MATRIX_MCFG_ULBT_128 0x00000007
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#endif
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/* Default Master Type */
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#define AT91_MATRIX_SCFG_DEFMSTR_TYPE_NONE 0x00000000
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#define AT91_MATRIX_SCFG_DEFMSTR_TYPE_LAST 0x00010000
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#define AT91_MATRIX_SCFG_DEFMSTR_TYPE_FIXED 0x00020000
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/* Fixed Index of Default Master */
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#if defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9263) || \
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defined(CONFIG_AT91SAM9M10G45)
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#define AT91_MATRIX_SCFG_FIXED_DEFMSTR(x) ((x & 0xf) << 18)
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#elif defined(CONFIG_AT91SAM9261) || defined(CONFIG_AT91SAM9260)
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#define AT91_MATRIX_SCFG_FIXED_DEFMSTR(x) ((x & 7) << 18)
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#endif
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/* Maximum Number of Allowed Cycles for a Burst */
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#if defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45)
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#define AT91_MATRIX_SCFG_SLOT_CYCLE(x) ((x & 0x1ff) << 0)
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#elif defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9261) || \
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defined(CONFIG_AT91SAM9263)
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#define AT91_MATRIX_SCFG_SLOT_CYCLE(x) ((x & 0xff) << 0)
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#endif
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/* Arbitration Type */
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#if defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9263)
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#define AT91_MATRIX_SCFG_ARBT_ROUND_ROBIN 0x00000000
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#define AT91_MATRIX_SCFG_ARBT_FIXED_PRIORITY 0x01000000
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#endif
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/* Master Remap Control Register */
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#if defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9263) || \
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defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45)
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/* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
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#define AT91_MATRIX_MRCR_RCB0 (1 << 0)
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/* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
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#define AT91_MATRIX_MRCR_RCB1 (1 << 1)
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#endif
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#if defined(CONFIG_AT91SAM9263) || defined(CONFIG_AT91SAM9G45) || \
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defined(CONFIG_AT91SAM9M10G45)
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#define AT91_MATRIX_MRCR_RCB2 0x00000004
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#define AT91_MATRIX_MRCR_RCB3 0x00000008
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#define AT91_MATRIX_MRCR_RCB4 0x00000010
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#define AT91_MATRIX_MRCR_RCB5 0x00000020
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#define AT91_MATRIX_MRCR_RCB6 0x00000040
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#define AT91_MATRIX_MRCR_RCB7 0x00000080
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#define AT91_MATRIX_MRCR_RCB8 0x00000100
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#endif
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#if defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45)
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#define AT91_MATRIX_MRCR_RCB9 0x00000200
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#define AT91_MATRIX_MRCR_RCB10 0x00000400
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#define AT91_MATRIX_MRCR_RCB11 0x00000800
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#endif
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/* TCM Configuration Register */
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#if defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45)
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/* Size of ITCM enabled memory block */
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#define AT91_MATRIX_TCMR_ITCM_0 0x00000000
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#define AT91_MATRIX_TCMR_ITCM_32 0x00000040
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/* Size of DTCM enabled memory block */
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#define AT91_MATRIX_TCMR_DTCM_0 0x00000000
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#define AT91_MATRIX_TCMR_DTCM_32 0x00000060
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#define AT91_MATRIX_TCMR_DTCM_64 0x00000070
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/* Wait state TCM register */
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#define AT91_MATRIX_TCMR_TCM_NO_WS 0x00000000
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#define AT91_MATRIX_TCMR_TCM_ONE_WS 0x00000800
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#endif
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#if defined(CONFIG_AT91SAM9263)
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/* Size of ITCM enabled memory block */
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#define AT91_MATRIX_TCMR_ITCM_0 0x00000000
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#define AT91_MATRIX_TCMR_ITCM_16 0x00000005
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#define AT91_MATRIX_TCMR_ITCM_32 0x00000006
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/* Size of DTCM enabled memory block */
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#define AT91_MATRIX_TCMR_DTCM_0 0x00000000
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#define AT91_MATRIX_TCMR_DTCM_16 0x00000050
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#define AT91_MATRIX_TCMR_DTCM_32 0x00000060
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#endif
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#if defined(CONFIG_AT91SAM9261)
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/* Size of ITCM enabled memory block */
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#define AT91_MATRIX_TCMR_ITCM_0 0x00000000
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#define AT91_MATRIX_TCMR_ITCM_16 0x00000005
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#define AT91_MATRIX_TCMR_ITCM_32 0x00000006
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#define AT91_MATRIX_TCMR_ITCM_64 0x00000007
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/* Size of DTCM enabled memory block */
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#define AT91_MATRIX_TCMR_DTCM_0 0x00000000
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#define AT91_MATRIX_TCMR_DTCM_16 0x00000050
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#define AT91_MATRIX_TCMR_DTCM_32 0x00000060
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#define AT91_MATRIX_TCMR_DTCM_64 0x00000070
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#endif
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#if defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45)
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/* Video Mode Configuration Register */
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#define AT91C_MATRIX_VDEC_SEL_OFF 0x00000000
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#define AT91C_MATRIX_VDEC_SEL_ON 0x00000001
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/* Write Protect Mode Register */
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#define AT91_MATRIX_WPMR_WP_WPDIS 0x00000000
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#define AT91_MATRIX_WPMR_WP_WPEN 0x00000001
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#define AT91_MATRIX_WPMR_WPKEY 0xFFFFFF00 /* Write Protect KEY */
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/* Write Protect Status Register */
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#define AT91_MATRIX_WPSR_NO_WPV 0x00000000
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#define AT91_MATRIX_WPSR_WPV 0x00000001
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#define AT91_MATRIX_WPSR_WPVSRC 0x00FFFF00 /* Write Protect Violation Source */
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#endif
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/* USB Pad Pull-Up Control Register */
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#if defined(CONFIG_AT91SAM9261)
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#define AT91_MATRIX_USBPUCR_PUON 0x40000000
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#endif
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#define AT91_MATRIX_PRA_M0(x) ((x & 3) << 0) /* Master 0 Priority Reg. A*/
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#define AT91_MATRIX_PRA_M1(x) ((x & 3) << 4) /* Master 1 Priority Reg. A*/
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#define AT91_MATRIX_PRA_M2(x) ((x & 3) << 8) /* Master 2 Priority Reg. A*/
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#define AT91_MATRIX_PRA_M3(x) ((x & 3) << 12) /* Master 3 Priority Reg. A*/
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#define AT91_MATRIX_PRA_M4(x) ((x & 3) << 16) /* Master 4 Priority Reg. A*/
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#define AT91_MATRIX_PRA_M5(x) ((x & 3) << 20) /* Master 5 Priority Reg. A*/
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#define AT91_MATRIX_PRA_M6(x) ((x & 3) << 24) /* Master 6 Priority Reg. A*/
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#define AT91_MATRIX_PRA_M7(x) ((x & 3) << 28) /* Master 7 Priority Reg. A*/
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#define AT91_MATRIX_PRB_M8(x) ((x & 3) << 0) /* Master 8 Priority Reg. B) */
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#define AT91_MATRIX_PRB_M9(x) ((x & 3) << 4) /* Master 9 Priority Reg. B) */
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#define AT91_MATRIX_PRB_M10(x) ((x & 3) << 8) /* Master 10 Priority Reg. B) */
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#endif
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