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Internal memory controller counters can reach a bad state after training in DDR4 mode if accumulated ECC or DBI mode is eanbled. Signed-off-by: York Sun <yorksun@freescale.com> |
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.. | ||
arm_ddr_gen3.c | ||
ctrl_regs.c | ||
ddr1_dimm_params.c | ||
ddr2_dimm_params.c | ||
ddr3_dimm_params.c | ||
ddr4_dimm_params.c | ||
fsl_ddr_gen4.c | ||
interactive.c | ||
lc_common_dimm_params.c | ||
main.c | ||
Makefile | ||
mpc85xx_ddr_gen1.c | ||
mpc85xx_ddr_gen2.c | ||
mpc85xx_ddr_gen3.c | ||
mpc86xx_ddr.c | ||
options.c | ||
util.c |