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https://github.com/brain-hackers/u-boot-brain
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791c174d58
If the clock framework provides the driver with valid clock, enable them, otherwise the SCIF might not work if the clock are not enabled prior to the driver probe. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
370 lines
7.8 KiB
C
370 lines
7.8 KiB
C
/*
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* SuperH SCIF device driver.
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* Copyright (C) 2013 Renesas Electronics Corporation
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* Copyright (C) 2007,2008,2010, 2014 Nobuhiro Iwamatsu
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* Copyright (C) 2002 - 2008 Paul Mundt
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <errno.h>
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#include <clk.h>
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#include <dm.h>
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#include <asm/io.h>
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#include <asm/processor.h>
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#include <serial.h>
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#include <linux/compiler.h>
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#include <dm/platform_data/serial_sh.h>
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#include "serial_sh.h"
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DECLARE_GLOBAL_DATA_PTR;
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#if defined(CONFIG_CPU_SH7760) || \
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defined(CONFIG_CPU_SH7780) || \
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defined(CONFIG_CPU_SH7785) || \
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defined(CONFIG_CPU_SH7786)
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static int scif_rxfill(struct uart_port *port)
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{
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return sci_in(port, SCRFDR) & 0xff;
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}
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#elif defined(CONFIG_CPU_SH7763)
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static int scif_rxfill(struct uart_port *port)
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{
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if ((port->mapbase == 0xffe00000) ||
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(port->mapbase == 0xffe08000)) {
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/* SCIF0/1*/
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return sci_in(port, SCRFDR) & 0xff;
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} else {
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/* SCIF2 */
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return sci_in(port, SCFDR) & SCIF2_RFDC_MASK;
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}
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}
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#elif defined(CONFIG_ARCH_SH7372)
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static int scif_rxfill(struct uart_port *port)
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{
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if (port->type == PORT_SCIFA)
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return sci_in(port, SCFDR) & SCIF_RFDC_MASK;
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else
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return sci_in(port, SCRFDR);
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}
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#else
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static int scif_rxfill(struct uart_port *port)
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{
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return sci_in(port, SCFDR) & SCIF_RFDC_MASK;
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}
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#endif
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static void sh_serial_init_generic(struct uart_port *port)
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{
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sci_out(port, SCSCR , SCSCR_INIT(port));
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sci_out(port, SCSCR , SCSCR_INIT(port));
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sci_out(port, SCSMR, 0);
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sci_out(port, SCSMR, 0);
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sci_out(port, SCFCR, SCFCR_RFRST|SCFCR_TFRST);
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sci_in(port, SCFCR);
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sci_out(port, SCFCR, 0);
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}
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static void
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sh_serial_setbrg_generic(struct uart_port *port, int clk, int baudrate)
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{
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if (port->clk_mode == EXT_CLK) {
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unsigned short dl = DL_VALUE(baudrate, clk);
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sci_out(port, DL, dl);
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/* Need wait: Clock * 1/dl * 1/16 */
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udelay((1000000 * dl * 16 / clk) * 1000 + 1);
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} else {
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sci_out(port, SCBRR, SCBRR_VALUE(baudrate, clk));
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}
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}
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static void handle_error(struct uart_port *port)
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{
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sci_in(port, SCxSR);
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sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
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sci_in(port, SCLSR);
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sci_out(port, SCLSR, 0x00);
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}
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static int serial_raw_putc(struct uart_port *port, const char c)
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{
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/* Tx fifo is empty */
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if (!(sci_in(port, SCxSR) & SCxSR_TEND(port)))
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return -EAGAIN;
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sci_out(port, SCxTDR, c);
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sci_out(port, SCxSR, sci_in(port, SCxSR) & ~SCxSR_TEND(port));
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return 0;
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}
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static int serial_rx_fifo_level(struct uart_port *port)
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{
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return scif_rxfill(port);
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}
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static int sh_serial_tstc_generic(struct uart_port *port)
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{
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if (sci_in(port, SCxSR) & SCIF_ERRORS) {
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handle_error(port);
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return 0;
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}
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return serial_rx_fifo_level(port) ? 1 : 0;
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}
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static int serial_getc_check(struct uart_port *port)
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{
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unsigned short status;
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status = sci_in(port, SCxSR);
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if (status & SCIF_ERRORS)
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handle_error(port);
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if (sci_in(port, SCLSR) & SCxSR_ORER(port))
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handle_error(port);
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return status & (SCIF_DR | SCxSR_RDxF(port));
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}
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static int sh_serial_getc_generic(struct uart_port *port)
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{
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unsigned short status;
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char ch;
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if (!serial_getc_check(port))
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return -EAGAIN;
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ch = sci_in(port, SCxRDR);
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status = sci_in(port, SCxSR);
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sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
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if (status & SCIF_ERRORS)
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handle_error(port);
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if (sci_in(port, SCLSR) & SCxSR_ORER(port))
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handle_error(port);
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return ch;
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}
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#ifdef CONFIG_DM_SERIAL
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static int sh_serial_pending(struct udevice *dev, bool input)
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{
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struct uart_port *priv = dev_get_priv(dev);
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return sh_serial_tstc_generic(priv);
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}
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static int sh_serial_putc(struct udevice *dev, const char ch)
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{
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struct uart_port *priv = dev_get_priv(dev);
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return serial_raw_putc(priv, ch);
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}
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static int sh_serial_getc(struct udevice *dev)
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{
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struct uart_port *priv = dev_get_priv(dev);
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return sh_serial_getc_generic(priv);
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}
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static int sh_serial_setbrg(struct udevice *dev, int baudrate)
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{
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struct sh_serial_platdata *plat = dev_get_platdata(dev);
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struct uart_port *priv = dev_get_priv(dev);
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sh_serial_setbrg_generic(priv, plat->clk, baudrate);
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return 0;
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}
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static int sh_serial_probe(struct udevice *dev)
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{
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struct sh_serial_platdata *plat = dev_get_platdata(dev);
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struct uart_port *priv = dev_get_priv(dev);
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priv->membase = (unsigned char *)plat->base;
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priv->mapbase = plat->base;
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priv->type = plat->type;
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priv->clk_mode = plat->clk_mode;
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sh_serial_init_generic(priv);
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return 0;
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}
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static const struct dm_serial_ops sh_serial_ops = {
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.putc = sh_serial_putc,
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.pending = sh_serial_pending,
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.getc = sh_serial_getc,
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.setbrg = sh_serial_setbrg,
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};
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#ifdef CONFIG_OF_CONTROL
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static const struct udevice_id sh_serial_id[] ={
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{.compatible = "renesas,sci", .data = PORT_SCI},
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{.compatible = "renesas,scif", .data = PORT_SCIF},
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{.compatible = "renesas,scifa", .data = PORT_SCIFA},
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{}
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};
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static int sh_serial_ofdata_to_platdata(struct udevice *dev)
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{
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struct sh_serial_platdata *plat = dev_get_platdata(dev);
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struct clk sh_serial_clk;
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fdt_addr_t addr;
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int ret;
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addr = fdtdec_get_addr(gd->fdt_blob, dev_of_offset(dev), "reg");
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if (addr == FDT_ADDR_T_NONE)
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return -EINVAL;
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plat->base = addr;
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ret = clk_get_by_name(dev, "fck", &sh_serial_clk);
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if (!ret) {
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ret = clk_enable(&sh_serial_clk);
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if (!ret)
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plat->clk = clk_get_rate(&sh_serial_clk);
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} else {
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plat->clk = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
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"clock", 1);
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}
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plat->type = dev_get_driver_data(dev);
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return 0;
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}
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#endif
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U_BOOT_DRIVER(serial_sh) = {
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.name = "serial_sh",
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.id = UCLASS_SERIAL,
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.of_match = of_match_ptr(sh_serial_id),
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.ofdata_to_platdata = of_match_ptr(sh_serial_ofdata_to_platdata),
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.platdata_auto_alloc_size = sizeof(struct sh_serial_platdata),
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.probe = sh_serial_probe,
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.ops = &sh_serial_ops,
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.flags = DM_FLAG_PRE_RELOC,
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.priv_auto_alloc_size = sizeof(struct uart_port),
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};
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#else /* CONFIG_DM_SERIAL */
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#if defined(CONFIG_CONS_SCIF0)
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# define SCIF_BASE SCIF0_BASE
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#elif defined(CONFIG_CONS_SCIF1)
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# define SCIF_BASE SCIF1_BASE
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#elif defined(CONFIG_CONS_SCIF2)
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# define SCIF_BASE SCIF2_BASE
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#elif defined(CONFIG_CONS_SCIF3)
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# define SCIF_BASE SCIF3_BASE
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#elif defined(CONFIG_CONS_SCIF4)
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# define SCIF_BASE SCIF4_BASE
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#elif defined(CONFIG_CONS_SCIF5)
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# define SCIF_BASE SCIF5_BASE
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#elif defined(CONFIG_CONS_SCIF6)
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# define SCIF_BASE SCIF6_BASE
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#elif defined(CONFIG_CONS_SCIF7)
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# define SCIF_BASE SCIF7_BASE
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#else
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# error "Default SCIF doesn't set....."
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#endif
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#if defined(CONFIG_SCIF_A)
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#define SCIF_BASE_PORT PORT_SCIFA
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#elif defined(CONFIG_SCI)
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#define SCIF_BASE_PORT PORT_SCI
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#else
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#define SCIF_BASE_PORT PORT_SCIF
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#endif
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static struct uart_port sh_sci = {
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.membase = (unsigned char *)SCIF_BASE,
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.mapbase = SCIF_BASE,
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.type = SCIF_BASE_PORT,
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#ifdef CONFIG_SCIF_USE_EXT_CLK
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.clk_mode = EXT_CLK,
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#endif
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};
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static void sh_serial_setbrg(void)
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{
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DECLARE_GLOBAL_DATA_PTR;
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struct uart_port *port = &sh_sci;
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sh_serial_setbrg_generic(port, CONFIG_SH_SCIF_CLK_FREQ, gd->baudrate);
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}
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static int sh_serial_init(void)
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{
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struct uart_port *port = &sh_sci;
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sh_serial_init_generic(port);
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serial_setbrg();
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return 0;
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}
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static void sh_serial_putc(const char c)
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{
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struct uart_port *port = &sh_sci;
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if (c == '\n') {
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while (1) {
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if (serial_raw_putc(port, '\r') != -EAGAIN)
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break;
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}
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}
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while (1) {
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if (serial_raw_putc(port, c) != -EAGAIN)
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break;
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}
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}
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static int sh_serial_tstc(void)
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{
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struct uart_port *port = &sh_sci;
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return sh_serial_tstc_generic(port);
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}
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static int sh_serial_getc(void)
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{
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struct uart_port *port = &sh_sci;
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int ch;
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while (1) {
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ch = sh_serial_getc_generic(port);
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if (ch != -EAGAIN)
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break;
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}
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return ch;
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}
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static struct serial_device sh_serial_drv = {
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.name = "sh_serial",
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.start = sh_serial_init,
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.stop = NULL,
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.setbrg = sh_serial_setbrg,
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.putc = sh_serial_putc,
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.puts = default_serial_puts,
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.getc = sh_serial_getc,
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.tstc = sh_serial_tstc,
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};
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void sh_serial_initialize(void)
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{
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serial_register(&sh_serial_drv);
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}
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__weak struct serial_device *default_serial_console(void)
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{
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return &sh_serial_drv;
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}
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#endif /* CONFIG_DM_SERIAL */
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