mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-03 08:43:45 +09:00
a2b1cff8b8
Move the setting for noc remap out of SPL code. Changing
noc remap inside SPL results in breaking back to BROM
boot.
Fixes commit c14fe2a8e1 ("rockchip: rk3188: Move SoC
one time setting into arch_cpu_init()").
Signed-off-by: Alexander Kochetkov <al.kochet@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
142 lines
3.0 KiB
C
142 lines
3.0 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2019 Rockchip Electronics Co., Ltd
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*/
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#include <common.h>
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#include <dm.h>
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#include <hang.h>
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#include <init.h>
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#include <log.h>
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#include <syscon.h>
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#include <asm/io.h>
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#include <asm/arch-rockchip/bootrom.h>
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#include <asm/arch-rockchip/clock.h>
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#include <asm/arch-rockchip/grf_rk3188.h>
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#include <asm/arch-rockchip/hardware.h>
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#include <linux/err.h>
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#define GRF_BASE 0x20008000
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const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
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[BROM_BOOTSOURCE_EMMC] = "/dwmmc@1021c000",
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[BROM_BOOTSOURCE_SD] = "/dwmmc@10214000",
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};
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#ifdef CONFIG_DEBUG_UART_BOARD_INIT
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void board_debug_uart_init(void)
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{
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/* Enable early UART on the RK3188 */
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struct rk3188_grf * const grf = (void *)GRF_BASE;
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enum {
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GPIO1B1_SHIFT = 2,
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GPIO1B1_MASK = 3,
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GPIO1B1_GPIO = 0,
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GPIO1B1_UART2_SOUT,
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GPIO1B1_JTAG_TDO,
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GPIO1B0_SHIFT = 0,
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GPIO1B0_MASK = 3,
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GPIO1B0_GPIO = 0,
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GPIO1B0_UART2_SIN,
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GPIO1B0_JTAG_TDI,
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};
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rk_clrsetreg(&grf->gpio1b_iomux,
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GPIO1B1_MASK << GPIO1B1_SHIFT |
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GPIO1B0_MASK << GPIO1B0_SHIFT,
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GPIO1B1_UART2_SOUT << GPIO1B1_SHIFT |
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GPIO1B0_UART2_SIN << GPIO1B0_SHIFT);
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}
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#endif
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#ifdef CONFIG_SPL_BUILD
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int arch_cpu_init(void)
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{
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struct rk3188_grf *grf;
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grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
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if (IS_ERR(grf)) {
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pr_err("grf syscon returned %ld\n", PTR_ERR(grf));
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return 0;
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}
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#ifdef CONFIG_ROCKCHIP_USB_UART
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rk_clrsetreg(&grf->uoc0_con[0],
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SIDDQ_MASK | UOC_DISABLE_MASK | COMMON_ON_N_MASK,
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1 << SIDDQ_SHIFT | 1 << UOC_DISABLE_SHIFT |
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1 << COMMON_ON_N_SHIFT);
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rk_clrsetreg(&grf->uoc0_con[2],
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SOFT_CON_SEL_MASK, 1 << SOFT_CON_SEL_SHIFT);
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rk_clrsetreg(&grf->uoc0_con[3],
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OPMODE_MASK | XCVRSELECT_MASK |
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TERMSEL_FULLSPEED_MASK | SUSPENDN_MASK,
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OPMODE_NODRIVING << OPMODE_SHIFT |
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XCVRSELECT_FSTRANSC << XCVRSELECT_SHIFT |
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1 << TERMSEL_FULLSPEED_SHIFT |
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1 << SUSPENDN_SHIFT);
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rk_clrsetreg(&grf->uoc0_con[0],
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BYPASSSEL_MASK | BYPASSDMEN_MASK,
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1 << BYPASSSEL_SHIFT | 1 << BYPASSDMEN_SHIFT);
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#endif
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return 0;
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}
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#endif
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__weak int rk3188_board_late_init(void)
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{
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return 0;
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}
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int rk_board_late_init(void)
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{
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struct rk3188_grf *grf;
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grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
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if (IS_ERR(grf)) {
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pr_err("grf syscon returned %ld\n", PTR_ERR(grf));
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return 0;
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}
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/* enable noc remap to mimic legacy loaders */
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rk_clrsetreg(&grf->soc_con0,
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NOC_REMAP_MASK << NOC_REMAP_SHIFT,
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NOC_REMAP_MASK << NOC_REMAP_SHIFT);
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return rk3188_board_late_init();
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}
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#ifdef CONFIG_SPL_BUILD
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static int setup_led(void)
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{
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#ifdef CONFIG_SPL_LED
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struct udevice *dev;
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char *led_name;
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int ret;
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led_name = fdtdec_get_config_string(gd->fdt_blob, "u-boot,boot-led");
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if (!led_name)
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return 0;
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ret = led_get_by_label(led_name, &dev);
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if (ret) {
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debug("%s: get=%d\n", __func__, ret);
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return ret;
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}
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ret = led_set_on(dev, 1);
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if (ret)
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return ret;
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#endif
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return 0;
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}
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void spl_board_init(void)
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{
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int ret;
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ret = setup_led();
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if (ret) {
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debug("LED ret=%d\n", ret);
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hang();
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}
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}
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#endif
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