mirror of
https://github.com/brain-hackers/u-boot-brain
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a257f6263b
On a real Malta the Super I/O needs to be configured before we are able to access the UARTs. This patch performs that configuration, setting up the UARTs in the same way that YAMON would. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
58 lines
1.0 KiB
C
58 lines
1.0 KiB
C
/*
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* Copyright (C) 2013 Gabor Juhos <juhosg@openwrt.org>
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#include <common.h>
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#include <netdev.h>
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#include <asm/addrspace.h>
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#include <asm/io.h>
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#include <asm/malta.h>
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#include <pci_gt64120.h>
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#include "superio.h"
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phys_size_t initdram(int board_type)
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{
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return CONFIG_SYS_MEM_SIZE;
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}
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int checkboard(void)
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{
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puts("Board: MIPS Malta CoreLV (Qemu)\n");
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return 0;
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}
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int board_eth_init(bd_t *bis)
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{
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return pci_eth_init(bis);
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}
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void _machine_restart(void)
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{
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void __iomem *reset_base;
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reset_base = (void __iomem *)CKSEG1ADDR(MALTA_RESET_BASE);
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__raw_writel(GORESET, reset_base);
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}
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int board_early_init_f(void)
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{
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/* setup FDC37M817 super I/O controller */
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malta_superio_init((void *)CKSEG1ADDR(MALTA_IO_PORT_BASE));
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return 0;
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}
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void pci_init_board(void)
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{
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set_io_port_base(CKSEG1ADDR(MALTA_IO_PORT_BASE));
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gt64120_pci_init((void *)CKSEG1ADDR(MALTA_GT_BASE),
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0x00000000, 0x00000000, CONFIG_SYS_MEM_SIZE,
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0x10000000, 0x10000000, 128 * 1024 * 1024,
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0x00000000, 0x00000000, 0x20000);
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}
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